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Help
Searched
refs:__offset_PP
(Results
1 - 2
of
2
) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
H
A
D
mdp5.xml.h
1303
static inline uint32_t
__offset_PP
(uint32_t idx)
in __offset_PP()
function
1313
static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 +
__offset_PP
(i0); }
in REG_MDP5_PP()
1315
static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 +
__offset_PP
(i0); }
in REG_MDP5_PP_TEAR_CHECK_EN()
1317
static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_CONFIG_VSYNC()
1327
static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_CONFIG_HEIGHT()
1329
static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_WRCOUNT()
1343
static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 +
__offset_PP
(i0); }
in REG_MDP5_PP_VSYNC_INIT_VAL()
1345
static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 +
__offset_PP
(i0); }
in REG_MDP5_PP_INT_COUNT_VAL()
1359
static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_THRESH()
1373
static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c +
__offset_PP
(i
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H
A
D
mdp5.xml.h
1314
static inline uint32_t
__offset_PP
(uint32_t idx)
in __offset_PP()
function
1324
static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 +
__offset_PP
(i0); }
in REG_MDP5_PP()
1326
static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 +
__offset_PP
(i0); }
in REG_MDP5_PP_TEAR_CHECK_EN()
1328
static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_CONFIG_VSYNC()
1338
static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_CONFIG_HEIGHT()
1340
static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_WRCOUNT()
1354
static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 +
__offset_PP
(i0); }
in REG_MDP5_PP_VSYNC_INIT_VAL()
1356
static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 +
__offset_PP
(i0); }
in REG_MDP5_PP_INT_COUNT_VAL()
1370
static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 +
__offset_PP
(i0); }
in REG_MDP5_PP_SYNC_THRESH()
1384
static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c +
__offset_PP
(i
[all...]
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