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Searched refs:__offset_INTF (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5.xml.h1743 static inline uint32_t __offset_INTF(uint32_t idx) in __offset_INTF() function
1754 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF()
1756 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF_TIMING_ENGINE_EN()
1758 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } in REG_MDP5_INTF_CONFIG()
1760 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); } in REG_MDP5_INTF_HSYNC_CTL()
1774 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1776 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1778 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_LEN_F0()
1780 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_LEN_F1()
1782 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5.xml.h1754 static inline uint32_t __offset_INTF(uint32_t idx) in __offset_INTF() function
1765 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF()
1767 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF_TIMING_ENGINE_EN()
1769 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } in REG_MDP5_INTF_CONFIG()
1771 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); } in REG_MDP5_INTF_HSYNC_CTL()
1785 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1787 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1789 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_LEN_F0()
1791 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_LEN_F1()
1793 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i
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