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Searched refs:_MMIO (Results 1 - 25 of 66) sorted by relevance

123

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h22 #define PERF_REG(offset) _MMIO(offset)
25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
32 #define RPM_CONFIG0 _MMIO(0xd00)
46 #define RPM_CONFIG1 _MMIO(0xd04)
50 #define RCP_CONFIG _MMIO(0xd08)
52 #define RC6_LOCATION _MMIO(0xd40)
54 #define RC6_CTX_BASE _MMIO(0xd48)
57 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
58 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
59 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(
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H A Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28)
12 #define RING_TAIL(base) _MMIO((base) + 0x30)
14 #define RING_HEAD(base) _MMIO((base) + 0x34)
18 #define RING_START(base) _MMIO((base) + 0x38)
19 #define RING_CTL(base) _MMIO((base) + 0x3c)
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
47 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
55 #define RING_MAX_IDLE(base) _MMIO((bas
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c61 #define RING_REG(base) _MMIO((base) + 0x28) in iterate_generic_mmio()
65 #define RING_REG(base) _MMIO((base) + 0x134) in iterate_generic_mmio()
69 #define RING_REG(base) _MMIO((base) + 0x6c) in iterate_generic_mmio()
72 MMIO_D(_MMIO(0x2148)); in iterate_generic_mmio()
74 MMIO_D(_MMIO(0x12198)); in iterate_generic_mmio()
83 #define RING_REG(base) _MMIO((base) + 0x29c) in iterate_generic_mmio()
95 MMIO_D(_MMIO(0x2124)); in iterate_generic_mmio()
96 MMIO_D(_MMIO(0x20dc)); in iterate_generic_mmio()
98 MMIO_D(_MMIO(0x2088)); in iterate_generic_mmio()
100 MMIO_D(_MMIO( in iterate_generic_mmio()
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H A Di915_perf_oa_regs.h11 #define GEN7_OACONTROL _MMIO(0x2360)
28 #define GEN8_OACTXID _MMIO(0x2364)
30 #define GEN8_OA_DEBUG _MMIO(0x2B04)
36 #define GEN8_OACONTROL _MMIO(0x2B00)
45 #define GEN8_OACTXCONTROL _MMIO(0x2360)
51 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
57 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
58 #define GEN8_OABUFFER _MMIO(0x2b14)
61 #define GEN7_OASTATUS1 _MMIO(0x2364)
67 #define GEN7_OASTATUS2 _MMIO(
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H A Dintel_mchbar_regs.h25 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
26 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
32 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
36 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
43 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
47 #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
48 #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
51 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
68 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
69 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BAS
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H A Di915_reg.h115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
147 #define _VGA_MSR_WRITE _MMIO(0x3c2)
156 #define DEBUG_RESET_I830 _MMIO(0x6070)
164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BAS
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_reg.h16 #define GUC_STATUS _MMIO(0xc000)
33 #define GUC_HEADER_INFO _MMIO(0xc014)
35 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
38 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
39 #define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4)
42 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
45 #define DMA_ADDR_0_LOW _MMIO(0xc300)
46 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
47 #define DMA_ADDR_1_LOW _MMIO(0xc308)
48 #define DMA_ADDR_1_HIGH _MMIO(
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_reg.h16 #define GUC_STATUS _MMIO(0xc000)
39 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
42 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
45 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
48 #define DMA_ADDR_0_LOW _MMIO(0xc300)
49 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
50 #define DMA_ADDR_1_LOW _MMIO(0xc308)
51 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
54 #define DMA_COPY_SIZE _MMIO(0xc310)
55 #define DMA_CTRL _MMIO(
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
82 #define TV_DAC _MMIO(0x68004)
133 #define TV_CSC_Y _MMIO(0x68010)
139 #define TV_CSC_Y2 _MMIO(0x68014)
150 #define TV_CSC_U _MMIO(0x68018)
156 #define TV_CSC_U2 _MMIO(0x6801c)
167 #define TV_CSC_V _MMIO(0x68020)
173 #define TV_CSC_V2 _MMIO(0x68024)
184 #define TV_CLR_KNOBS _MMIO(0x68028)
198 #define TV_CLR_LEVEL _MMIO(
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H A Dintel_combo_phy_regs.h27 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
31 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
48 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
56 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
59 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
61 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
73 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
76 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
78 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
90 #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AU
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H A Dintel_vdsc_regs.h12 #define DSS_CTL1 _MMIO(0x67400)
23 #define DSS_CTL2 _MMIO(0x67404)
76 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
77 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
100 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
101 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
114 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
115 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
129 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
130 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(
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H A Dintel_dsb_regs.h15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
40 #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
51 #define DSB_CURRENT_HEAD(pipe, id) _MMIO(DSBSL_INSTANC
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H A Dintel_dmc_regs.h11 #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
46 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))
51 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))
67 #define DMC_SSP_BASE _MMIO(0x8F074)
68 #define DMC_HTP_SKL _MMIO(0x8F004)
69 #define DMC_LAST_WRITE _MMIO(0x8F034)
89 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
90 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
91 #define BXT_DMC_DC3_DC5_COUNT _MMIO(
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H A Dintel_display_reg_defs.h25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
27 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
28 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
29 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
30 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
32 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
33 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
39 #define _MMIO_PIPE2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->pipe_offsets[(pipe)] - \
42 #define _MMIO_TRANS2(tran, reg) _MMIO(DISPLAY_INF
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H A Dintel_backlight_regs.h24 #define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */
47 #define BLC_PWM_CTL _MMIO(0x61254)
69 #define BLC_HIST_CTL _MMIO(0x61260)
74 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
75 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
77 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
81 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
85 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
106 #define UTIL_PIN_CTL _MMIO(0x48400)
H A Dskl_watermark_regs.h31 #define MBUS_UBOX_CTL _MMIO(0x4503C)
32 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
33 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
35 #define MBUS_CTL _MMIO(0x4438C)
75 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
84 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
90 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
96 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
102 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
139 #define DBUF_CTL_S(slice) _MMIO(_PIC
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H A Dintel_gmbus_regs.h13 #define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
30 #define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
40 #define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
57 #define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
67 #define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
70 #define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
78 #define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
H A Dintel_audio_regs.h11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
39 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
47 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
112 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
113 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
124 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
127 #define AUD_FREQ_CNTRL _MMIO(0x65900)
128 #define AUD_PIN_BUF_CTL _MMIO(
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H A Dintel_fdi_regs.h11 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
13 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
14 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
15 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
16 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
17 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
19 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
148 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
149 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H A Dreg.h71 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
72 (_MMIO(0x50090))) : \
73 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
74 (_MMIO(0x50098))) : \
75 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
76 (_MMIO(0x5009C))) : \
77 (_MMIO(0x50080))))); })
117 #define PCH_GPIO_BASE _MMIO(0xc5010)
119 #define PCH_GMBUS0 _MMIO(0xc5100)
120 #define PCH_GMBUS1 _MMIO(
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H A Dhandlers.c57 #define PCH_PP_STATUS _MMIO(0xc7200)
58 #define PCH_PP_CONTROL _MMIO(0xc7204)
59 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
60 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
61 #define PCH_PP_DIVISOR _MMIO(0xc7210)
718 _MMIO(0xd80),
719 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
720 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
721 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
722 PS_INVOCATION_COUNT, //_MMIO(
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_reg.h115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) macro
187 #define INVALID_MMIO_REG _MMIO(0)
234 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
235 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
236 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
237 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
238 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
242 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIC
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Dreg.h72 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
73 (_MMIO(0x50090))) : \
74 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
75 (_MMIO(0x50098))) : \
76 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
77 (_MMIO(0x5009C))) : \
78 (_MMIO(0x50080))))); })
118 #define PCH_GPIO_BASE _MMIO(0xc5010)
120 #define PCH_GMBUS0 _MMIO(0xc5100)
121 #define PCH_GMBUS1 _MMIO(
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H A Dhandlers.c44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
467 _MMIO(0xd80),
468 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
469 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
470 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
471 PS_INVOCATION_COUNT, //_MMIO(
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.h38 #define RING_ELSP(base) _MMIO((base) + 0x230)
39 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
40 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
41 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
47 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
48 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
49 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)

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