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Searched refs:XAXIDMA_RX_CR_OFFSET (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/ni/
H A Dnixge.c31 #define XAXIDMA_RX_CR_OFFSET 0x30 /* Channel control */ macro
344 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
354 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
373 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
374 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, in nixge_hw_dma_bd_init()
417 __nixge_device_reset(priv, XAXIDMA_RX_CR_OFFSET); in nixge_device_reset()
689 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_poll()
691 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_poll()
729 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_tx_irq()
733 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, c in nixge_tx_irq()
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/ni/
H A Dnixge.c30 #define XAXIDMA_RX_CR_OFFSET 0x30 /* Channel control */ macro
344 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
354 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
373 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
374 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, in nixge_hw_dma_bd_init()
417 __nixge_device_reset(priv, XAXIDMA_RX_CR_OFFSET); in nixge_device_reset()
689 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_poll()
691 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_poll()
729 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_tx_irq()
733 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, c in nixge_tx_irq()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_main.c300 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_bd_init()
310 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_dma_bd_init()
329 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_bd_init()
330 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, in axienet_dma_bd_init()
977 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_tx_irq()
981 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_tx_irq()
1027 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_rx_irq()
1031 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_rx_irq()
1173 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_stop()
1175 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, c in axienet_stop()
[all...]
H A Dxilinx_axienet.h79 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */ macro
/kernel/linux/linux-6.6/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_main.c244 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); in axienet_dma_start()
263 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); in axienet_dma_start()
545 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_stop()
547 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_dma_stop()
1003 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); in axienet_rx_poll()
1088 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_rx_irq()
1419 data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_ethtools_get_regs()
H A Dxilinx_axienet.h79 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */ macro

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