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Searched refs:WREG32_SOC15_RLC (Results 1 - 11 of 11) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c74 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
80 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
91 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
96 WREG32_SOC15_RLC( in gfxhub_v1_0_init_system_aperture_regs()
137 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
154 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
159 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
171 WREG32_SOC15_RLC(G in gfxhub_v1_0_init_cache_regs()
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H A Dgfx_v9_0.c2015 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
2027 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
2514 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in gfx_v9_0_init_compute_vmid()
2515 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
2589 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2590 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); in gfx_v9_0_constants_init()
2596 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2601 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); in gfx_v9_0_constants_init()
3138 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
3334 WREG32_SOC15_RLC(G in gfx_v9_0_cp_compute_enable()
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H A Dsoc15_common.h121 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ macro
H A Dgfx_v10_0.c4858 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, in gfx_v10_0_init_csb()
4860 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, in gfx_v10_0_init_csb()
4862 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5479 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c96 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
97 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
98 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
102 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
115 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
120 WREG32_SOC15_RLC( in gfxhub_v1_0_init_system_aperture_regs()
171 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
188 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
193 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
205 WREG32_SOC15_RLC(G in gfxhub_v1_0_init_cache_regs()
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H A Dgfxhub_v1_2.c133 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0); in gfxhub_v1_2_xcc_init_system_aperture_regs()
134 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_2_xcc_init_system_aperture_regs()
135 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_2_xcc_init_system_aperture_regs()
139 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_2_xcc_init_system_aperture_regs()
152 WREG32_SOC15_RLC(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_system_aperture_regs()
157 WREG32_SOC15_RLC(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_system_aperture_regs()
216 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_init_tlb_regs()
237 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
242 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
254 WREG32_SOC15_RLC(G in gfxhub_v1_2_xcc_init_cache_regs()
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H A Dmmhub_v2_0.c207 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
209 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
214 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
225 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_0_init_system_aperture_regs()
226 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_0_init_system_aperture_regs()
227 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_0_init_system_aperture_regs()
334 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); in mmhub_v2_0_enable_system_domain()
H A Dgfx_v9_4_3.c552 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_ind()
564 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_regs()
926 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); in gfx_v9_4_3_xcc_init_compute_vmid()
927 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v9_4_3_xcc_init_compute_vmid()
932 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v9_4_3_xcc_init_compute_vmid()
982 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
984 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
999 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1385 WREG32_SOC15_RLC(G in gfx_v9_4_3_xcc_cp_compute_enable()
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H A Dgfx_v9_0.c1744 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
1756 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
2328 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in gfx_v9_0_init_compute_vmid()
2329 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
2403 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2404 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); in gfx_v9_0_constants_init()
2410 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2415 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); in gfx_v9_0_constants_init()
2962 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
3165 WREG32_SOC15_RLC(G in gfx_v9_0_cp_compute_enable()
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H A Dsoc15_common.h172 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ macro
H A Dgfx_v10_0.c5036 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, in gfx_v10_0_init_csb()
5038 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, in gfx_v10_0_init_csb()
5040 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5665 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()

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