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Searched refs:WR (Results 1 - 25 of 26) sorted by relevance

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/kernel/linux/linux-5.10/drivers/block/paride/
H A Dbpck.c105 #define WR(r,v) bpck_write_regr(pi,2,r,v) macro
114 case 0: WR(4,0x40); in bpck_write_block()
117 WR(4,0); in bpck_write_block()
120 case 1: WR(4,0x50); in bpck_write_block()
123 WR(4,0x10); in bpck_write_block()
126 case 2: WR(4,0x48); in bpck_write_block()
130 WR(4,8); in bpck_write_block()
133 case 3: WR(4,0x48); in bpck_write_block()
137 WR(4,8); in bpck_write_block()
140 case 4: WR( in bpck_write_block()
[all...]
H A Depia.c104 #define WR(r,v) epia_write_regr(pi,0,r,v) macro
124 WR(0x86,8); in epia_connect()
129 { /* WR(0x84,0x10); */ in epia_disconnect()
175 case 3: if (count > 512) WR(0x84,3); in epia_read_block()
178 w2(4); WR(0x84,0); in epia_read_block()
181 case 4: if (count > 512) WR(0x84,3); in epia_read_block()
184 w2(4); WR(0x84,0); in epia_read_block()
187 case 5: if (count > 512) WR(0x84,3); in epia_read_block()
190 w2(4); WR(0x84,0); in epia_read_block()
215 case 3: if (count < 512) WR( in epia_write_block()
[all...]
H A Depat.c200 #define WR(r,v) epat_write_regr(pi,2,r,v) macro
224 WR(0x8,0x12);WR(0xc,0x14);WR(0x12,0x10); in epat_connect()
225 WR(0xe,0xf);WR(0xf,4); in epat_connect()
226 /* WR(0xe,0xa);WR(0xf,4); */ in epat_connect()
227 WR(0xe,0xd);WR( in epat_connect()
[all...]
/kernel/linux/linux-6.6/drivers/ata/pata_parport/
H A Dbpck.c93 #define WR(r,v) bpck_write_regr(pi,2,r,v) macro
103 WR(4, 0x40); in bpck_write_block()
109 WR(4, 0); in bpck_write_block()
113 WR(4, 0x50); in bpck_write_block()
119 WR(4, 0x10); in bpck_write_block()
123 WR(4, 0x48); in bpck_write_block()
128 WR(4, 8); in bpck_write_block()
132 WR(4, 0x48); in bpck_write_block()
137 WR(4, 8); in bpck_write_block()
141 WR( in bpck_write_block()
[all...]
H A Depia.c94 #define WR(r, v) epia_write_regr(pi, 0, r, v) macro
114 WR(0x86, 8); in epia_connect()
119 /* WR(0x84,0x10); */ in epia_disconnect()
167 WR(0x84, 3); in epia_read_block()
171 w2(4); WR(0x84, 0); in epia_read_block()
175 WR(0x84, 3); in epia_read_block()
179 w2(4); WR(0x84, 0); in epia_read_block()
183 WR(0x84, 3); in epia_read_block()
187 w2(4); WR(0x84, 0); in epia_read_block()
215 WR( in epia_write_block()
[all...]
H A Depat.c208 #define WR(r, v) epat_write_regr(pi, 2, r, v) macro
237 WR(0x8, 0x12); in epat_connect()
238 WR(0xc, 0x14); in epat_connect()
239 WR(0x12, 0x10); in epat_connect()
240 WR(0xe, 0xf); in epat_connect()
241 WR(0xf, 4); in epat_connect()
242 /* WR(0xe,0xa);WR(0xf,4); */ in epat_connect()
243 WR(0xe, 0xd); in epat_connect()
244 WR( in epat_connect()
[all...]
/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-au1550.c44 static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) in WR() function
105 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); in do_address()
108 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); in do_address()
124 WR(adap, PSC_SMBTXRX, addr); in do_address()
125 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); in do_address()
169 WR(adap, PSC_SMBTXRX, 0); in i2c_read()
177 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); in i2c_read()
197 WR(adap, PSC_SMBTXRX, data); in i2c_write()
206 WR(adap, PSC_SMBTXRX, data); in i2c_write()
219 WR(ada in au1550_xfer()
[all...]
/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-au1550.c44 static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) in WR() function
105 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); in do_address()
108 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); in do_address()
124 WR(adap, PSC_SMBTXRX, addr); in do_address()
125 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); in do_address()
169 WR(adap, PSC_SMBTXRX, 0); in i2c_read()
177 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); in i2c_read()
197 WR(adap, PSC_SMBTXRX, data); in i2c_write()
206 WR(adap, PSC_SMBTXRX, data); in i2c_write()
219 WR(ada in au1550_xfer()
[all...]
/kernel/linux/linux-5.10/include/linux/ceph/
H A Drados.h228 f(WRITE, __CEPH_OSD_OP(WR, DATA, 1), "write") \
229 f(WRITEFULL, __CEPH_OSD_OP(WR, DATA, 2), "writefull") \
230 f(TRUNCATE, __CEPH_OSD_OP(WR, DATA, 3), "truncate") \
231 f(ZERO, __CEPH_OSD_OP(WR, DATA, 4), "zero") \
232 f(DELETE, __CEPH_OSD_OP(WR, DATA, 5), "delete") \
235 f(APPEND, __CEPH_OSD_OP(WR, DATA, 6), "append") \
236 f(SETTRUNC, __CEPH_OSD_OP(WR, DATA, 8), "settrunc") \
237 f(TRIMTRUNC, __CEPH_OSD_OP(WR, DATA, 9), "trimtrunc") \
240 f(TMAPPUT, __CEPH_OSD_OP(WR, DATA, 11), "tmapput") \
243 f(CREATE, __CEPH_OSD_OP(WR, DAT
[all...]
/kernel/linux/linux-6.6/include/linux/ceph/
H A Drados.h228 f(WRITE, __CEPH_OSD_OP(WR, DATA, 1), "write") \
229 f(WRITEFULL, __CEPH_OSD_OP(WR, DATA, 2), "writefull") \
230 f(TRUNCATE, __CEPH_OSD_OP(WR, DATA, 3), "truncate") \
231 f(ZERO, __CEPH_OSD_OP(WR, DATA, 4), "zero") \
232 f(DELETE, __CEPH_OSD_OP(WR, DATA, 5), "delete") \
235 f(APPEND, __CEPH_OSD_OP(WR, DATA, 6), "append") \
236 f(SETTRUNC, __CEPH_OSD_OP(WR, DATA, 8), "settrunc") \
237 f(TRIMTRUNC, __CEPH_OSD_OP(WR, DATA, 9), "trimtrunc") \
240 f(TMAPPUT, __CEPH_OSD_OP(WR, DATA, 11), "tmapput") \
243 f(CREATE, __CEPH_OSD_OP(WR, DAT
[all...]
/kernel/linux/linux-5.10/sound/soc/au1x/
H A Dac97c.c77 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) in WR() function
103 WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ); in au1xac97c_ac97_read()
142 WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v)); in au1xac97c_ac97_write()
159 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN); in au1xac97c_ac97_warm_reset()
161 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG); in au1xac97c_ac97_warm_reset()
162 WR(ctx, AC97_CONFIG, ctx->cfg); in au1xac97c_ac97_warm_reset()
170 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS); in au1xac97c_ac97_cold_reset()
172 WR(ctx, AC97_CONFIG, ctx->cfg); in au1xac97c_ac97_cold_reset()
266 WR(ctx, AC97_ENABLE, EN_D | EN_CE); in au1xac97c_drvprobe()
267 WR(ct in au1xac97c_drvprobe()
[all...]
H A Di2sc.c75 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) in WR() function
146 WR(ctx, I2S_ENABLE, EN_D | EN_CE); in au1xi2s_trigger()
147 WR(ctx, I2S_ENABLE, EN_CE); in au1xi2s_trigger()
149 WR(ctx, I2S_CFG, ctx->cfg); in au1xi2s_trigger()
154 WR(ctx, I2S_CFG, ctx->cfg); in au1xi2s_trigger()
155 WR(ctx, I2S_ENABLE, EN_D); /* power off */ in au1xi2s_trigger()
278 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */ in au1xi2s_drvremove()
288 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */ in au1xi2s_drvsuspend()
/kernel/linux/linux-6.6/sound/soc/au1x/
H A Dac97c.c77 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) in WR() function
103 WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ); in au1xac97c_ac97_read()
142 WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v)); in au1xac97c_ac97_write()
159 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN); in au1xac97c_ac97_warm_reset()
161 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG); in au1xac97c_ac97_warm_reset()
162 WR(ctx, AC97_CONFIG, ctx->cfg); in au1xac97c_ac97_warm_reset()
170 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS); in au1xac97c_ac97_cold_reset()
172 WR(ctx, AC97_CONFIG, ctx->cfg); in au1xac97c_ac97_cold_reset()
267 WR(ctx, AC97_ENABLE, EN_D | EN_CE); in au1xac97c_drvprobe()
268 WR(ct in au1xac97c_drvprobe()
[all...]
H A Di2sc.c75 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) in WR() function
146 WR(ctx, I2S_ENABLE, EN_D | EN_CE); in au1xi2s_trigger()
147 WR(ctx, I2S_ENABLE, EN_CE); in au1xi2s_trigger()
149 WR(ctx, I2S_CFG, ctx->cfg); in au1xi2s_trigger()
154 WR(ctx, I2S_CFG, ctx->cfg); in au1xi2s_trigger()
155 WR(ctx, I2S_ENABLE, EN_D); /* power off */ in au1xi2s_trigger()
279 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */ in au1xi2s_drvremove()
287 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */ in au1xi2s_drvsuspend()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
84 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
90 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr3_calc()
102 WR = ramxlat(ramddr3_wr, WR); in nvkm_sddr3_calc()
103 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
107 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr3_calc()
H A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
68 WR = ram->next->bios.timing_10_WR; in nvkm_sddr2_calc()
74 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr2_calc()
87 WR = ramxlat(ramddr2_wr, WR); in nvkm_sddr2_calc()
88 if (CL < 0 || WR < 0) in nvkm_sddr2_calc()
92 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr2_calc()
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
79 WR = ram->next->bios.timing_10_WR; in nvkm_gddr3_calc()
87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr3_calc()
103 WR = ramxlat(ramgddr3_wr_lo, WR); in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
115 ram->mr[1] |= (WR & 0x03) << 4; in nvkm_gddr3_calc()
116 ram->mr[1] |= (WR & 0x04) << 5; in nvkm_gddr3_calc()
H A Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local
60 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()
73 WR -= 4; in nvkm_gddr5_calc()
76 ram->mr[0] |= (WR & 0x0f) << 8; in nvkm_gddr5_calc()
118 ram->mr[8] |= (WR & 0x10) >> 3; in nvkm_gddr5_calc()
H A Dramnv50.c110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
177 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); in nv50_ram_timing_read()
H A Dramgt215.c375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
84 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
90 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr3_calc()
102 WR = ramxlat(ramddr3_wr, WR); in nvkm_sddr3_calc()
103 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
107 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr3_calc()
H A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
68 WR = ram->next->bios.timing_10_WR; in nvkm_sddr2_calc()
74 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr2_calc()
87 WR = ramxlat(ramddr2_wr, WR); in nvkm_sddr2_calc()
88 if (CL < 0 || WR < 0) in nvkm_sddr2_calc()
92 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr2_calc()
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
79 WR = ram->next->bios.timing_10_WR; in nvkm_gddr3_calc()
87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr3_calc()
103 WR = ramxlat(ramgddr3_wr_lo, WR); in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
115 ram->mr[1] |= (WR & 0x03) << 4; in nvkm_gddr3_calc()
116 ram->mr[1] |= (WR & 0x04) << 5; in nvkm_gddr3_calc()
H A Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local
60 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()
73 WR -= 4; in nvkm_gddr5_calc()
76 ram->mr[0] |= (WR & 0x0f) << 8; in nvkm_gddr5_calc()
118 ram->mr[8] |= (WR & 0x10) >> 3; in nvkm_gddr5_calc()
H A Dramnv50.c110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
176 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); in nv50_ram_timing_read()

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