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Searched refs:VCO_REF_CLK_RATE (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/
H A Ddsi_pll_28nm.c35 #define VCO_REF_CLK_RATE 19200000 macro
161 rem = rate % VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_set_rate()
165 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()
166 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()
170 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()
171 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()
260 u32 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_recalc_rate()
268 ref_clk += (doubler * VCO_REF_CLK_RATE); in dsi_pll_28nm_clk_recalc_rate()
H A Ddsi_pll_28nm_8960.c42 #define VCO_REF_CLK_RATE 27000000 macro
120 val = VCO_REF_CLK_RATE / 10; in dsi_pll_28nm_clk_set_rate()
H A Ddsi_pll_10nm.c42 #define VCO_REF_CLK_RATE 19200000 macro
326 pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; in dsi_pll_10nm_vco_set_rate()
H A Ddsi_pll_7nm.c42 #define VCO_REF_CLK_RATE 19200000 macro
344 pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; in dsi_pll_7nm_vco_set_rate()
H A Ddsi_pll_14nm.c35 #define VCO_REF_CLK_RATE 19200000 macro
586 pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; in dsi_pll_14nm_vco_set_rate()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm.c34 #define VCO_REF_CLK_RATE 19200000 macro
148 rem = rate % VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_set_rate()
152 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()
153 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()
157 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()
158 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()
247 u32 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_recalc_rate()
255 ref_clk += (doubler * VCO_REF_CLK_RATE); in dsi_pll_28nm_clk_recalc_rate()
H A Ddsi_phy_14nm.c37 #define VCO_REF_CLK_RATE 19200000 macro
172 DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE); in pll_14nm_ssc_calc()
175 period = (u32)VCO_REF_CLK_RATE / 1000; in pll_14nm_ssc_calc()
184 ref = VCO_REF_CLK_RATE; in pll_14nm_ssc_calc()
211 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_dec_frac_calc()
254 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_calc_vco_count()
542 if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) in dsi_pll_14nm_vco_prepare()
543 dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); in dsi_pll_14nm_vco_prepare()
H A Ddsi_phy_10nm.c39 #define VCO_REF_CLK_RATE 19200000 macro
116 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac()
161 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; in dsi_pll_calc_ssc()
425 u64 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_10nm_vco_recalc_rate()
530 VCO_REF_CLK_RATE); in dsi_10nm_pll_restore_state()
H A Ddsi_phy_7nm.c39 #define VCO_REF_CLK_RATE 19200000 macro
112 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac()
168 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; in dsi_pll_calc_ssc()
474 u64 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_7nm_vco_recalc_rate()
579 VCO_REF_CLK_RATE); in dsi_7nm_pll_restore_state()
H A Ddsi_phy_28nm_8960.c42 #define VCO_REF_CLK_RATE 27000000 macro
103 val = VCO_REF_CLK_RATE / 10; in dsi_pll_28nm_clk_set_rate()

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