VC5_OUT_DIV_CONTROL (reference) in projects: kernel - OpenGrok search results

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Searched refs:VC5_OUT_DIV_CONTROL (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/
H A D	clk-versaclock5.c	`78 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) macro 609 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); in vc5_clk_out_prepare() 613 VC5_OUT_DIV_CONTROL(hwdata->num), in vc5_clk_out_prepare() 660 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); in vc5_clk_out_get_parent() 694 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), in vc5_clk_out_set_parent()`
/kernel/linux/linux-6.6/drivers/clk/
H A D	clk-versaclock5.c	`77 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) macro 626 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); in vc5_clk_out_prepare() 633 VC5_OUT_DIV_CONTROL(hwdata->num), in vc5_clk_out_prepare() 685 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); in vc5_clk_out_get_parent() 722 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), in vc5_clk_out_set_parent()`

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