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Searched refs:V4L2_DV_VSYNC_POS_POL (Results 1 - 25 of 25) sorted by relevance

/kernel/linux/linux-5.10/include/uapi/linux/
H A Dv4l2-dv-timings.h87 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
105 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
115 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
124 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
134 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
153 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
163 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
173 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
[all...]
H A Dvideodev2.h1468 #define V4L2_DV_VSYNC_POS_POL 0x00000001 macro
/kernel/linux/linux-6.6/include/uapi/linux/
H A Dv4l2-dv-timings.h78 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
87 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
106 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
115 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
125 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
135 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
154 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
164 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
[all...]
H A Dvideodev2.h1548 #define V4L2_DV_VSYNC_POS_POL 0x00000001 macro
/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/
H A Dv4l2-dv-timings.h36 #define V4L2_DV_BT_CEA_1280X720P24 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
38 #define V4L2_DV_BT_CEA_1280X720P25 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
40 #define V4L2_DV_BT_CEA_1280X720P30 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
42 #define V4L2_DV_BT_CEA_1280X720P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
44 #define V4L2_DV_BT_CEA_1280X720P60 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
46 #define V4L2_DV_BT_CEA_1920X1080P24 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
48 #define V4L2_DV_BT_CEA_1920X1080P25 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
50 #define V4L2_DV_BT_CEA_1920X1080P30 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
52 #define V4L2_DV_BT_CEA_1920X1080I50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 1, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
54 #define V4L2_DV_BT_CEA_1920X1080P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 14850000
[all...]
H A Dvideodev2.h756 #define V4L2_DV_VSYNC_POS_POL 0x00000001 macro
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
H A Dv4l2-dv-timings.h59 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
67 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
75 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
84 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
92 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
101 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
110 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
118 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
127 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
136 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
[all...]
H A Dvideodev2.h803 #define V4L2_DV_VSYNC_POS_POL 0x00000001 macro
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
H A Dv4l2-dv-timings.h36 #define V4L2_DV_BT_CEA_1280X720P24 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
38 #define V4L2_DV_BT_CEA_1280X720P25 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
40 #define V4L2_DV_BT_CEA_1280X720P30 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
42 #define V4L2_DV_BT_CEA_1280X720P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
44 #define V4L2_DV_BT_CEA_1280X720P60 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
46 #define V4L2_DV_BT_CEA_1920X1080P24 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
48 #define V4L2_DV_BT_CEA_1920X1080P25 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
50 #define V4L2_DV_BT_CEA_1920X1080P30 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
52 #define V4L2_DV_BT_CEA_1920X1080I50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 1, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
54 #define V4L2_DV_BT_CEA_1920X1080P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1920, 1080, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 14850000
[all...]
H A Dvideodev2.h756 #define V4L2_DV_VSYNC_POS_POL 0x00000001 macro
/kernel/linux/linux-5.10/drivers/media/v4l2-core/
H A Dv4l2-dv-timings.c331 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", in v4l2_print_dv_timings()
336 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", in v4l2_print_dv_timings()
507 if (polarities == V4L2_DV_VSYNC_POS_POL) in v4l2_detect_cvt()
725 if (polarities == V4L2_DV_VSYNC_POS_POL) in v4l2_detect_gtf()
/kernel/linux/linux-6.6/drivers/media/v4l2-core/
H A Dv4l2-dv-timings.c331 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", in v4l2_print_dv_timings()
336 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", in v4l2_print_dv_timings()
507 if (polarities == V4L2_DV_VSYNC_POS_POL) in v4l2_detect_cvt()
725 if (polarities == V4L2_DV_VSYNC_POS_POL) in v4l2_detect_gtf()
/kernel/linux/linux-6.6/drivers/media/platform/aspeed/
H A Daspeed-video.c865 ~V4L2_DV_VSYNC_POS_POL; in aspeed_video_check_and_set_polarity()
869 V4L2_DV_VSYNC_POS_POL; in aspeed_video_check_and_set_polarity()
1000 det->polarities &= ~V4L2_DV_VSYNC_POS_POL; in aspeed_video_get_timings()
1002 det->polarities |= V4L2_DV_VSYNC_POS_POL; in aspeed_video_get_timings()
1008 if (det->polarities & V4L2_DV_VSYNC_POS_POL) { in aspeed_video_get_timings()
/kernel/linux/linux-5.10/drivers/media/i2c/
H A Dths8200.c340 if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { in ths8200_setup()
H A Dadv7604.c1393 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1398 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1601 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv76xx_query_dv_timings()
H A Dadv7842.c1447 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1452 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1585 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv7842_query_dv_timings()
H A Dadv7511-v4l2.c1054 ((bt->polarities & V4L2_DV_VSYNC_POS_POL) ? 0 : 0x40) | in adv7511_s_dv_timings()
/kernel/linux/linux-6.6/drivers/media/i2c/
H A Dths8200.c340 if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { in ths8200_setup()
H A Dadv7604.c1407 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1412 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1615 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv76xx_query_dv_timings()
H A Dadv7842.c1435 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1440 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1573 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv7842_query_dv_timings()
H A Dadv7511-v4l2.c1020 ((bt->polarities & V4L2_DV_VSYNC_POS_POL) ? 0 : 0x40) | in adv7511_s_dv_timings()
H A Dtda1997x.c1152 timings->bt.polarities = vsync_pos ? V4L2_DV_VSYNC_POS_POL : 0; in tda1997x_detect_std()
/kernel/linux/linux-5.10/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c317 bt->polarities = (polarity & BIT(4) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv748x_hdmi_query_dv_timings()
/kernel/linux/linux-6.6/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c327 bt->polarities = (polarity & BIT(4) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv748x_hdmi_query_dv_timings()
/kernel/linux/linux-5.10/drivers/media/platform/
H A Daspeed-video.c688 ~V4L2_DV_VSYNC_POS_POL; in aspeed_video_check_and_set_polarity()
692 V4L2_DV_VSYNC_POS_POL; in aspeed_video_check_and_set_polarity()

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