| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| H A D | smumgr.h | 48 UvdBootLevel, enumerator
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| H A D | smu7_fusion.h | 240 uint8_t UvdBootLevel; member
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| H A D | smu7_discrete.h | 337 uint8_t UvdBootLevel; member
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| H A D | smu75_discrete.h | 303 uint8_t UvdBootLevel; member
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| H A D | smu74_discrete.h | 297 uint8_t UvdBootLevel; member
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| H A D | smu72_discrete.h | 279 uint8_t UvdBootLevel; member
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| H A D | smu73_discrete.h | 263 uint8_t UvdBootLevel; member
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smumgr.h | 48 UvdBootLevel, enumerator
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| H A D | smu7_fusion.h | 231 uint8_t UvdBootLevel; member
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| H A D | smu7_discrete.h | 337 uint8_t UvdBootLevel; member
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| H A D | smu75_discrete.h | 303 uint8_t UvdBootLevel; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | vegam_smumgr.c | 338 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()
340 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table()
343 UvdBootLevel); in vegam_update_uvd_smc_table()
349 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in vegam_update_uvd_smc_table()
359 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in vegam_update_uvd_smc_table()
1322 table->UvdBootLevel = 0; in vegam_populate_smc_uvd_level()
2188 case UvdBootLevel: in vegam_get_offsetof()
2189 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel); in vegam_get_offsetof()
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| H A D | fiji_smumgr.c | 1566 table->UvdBootLevel = 0; in fiji_populate_smc_uvd_level()
2328 case UvdBootLevel: in fiji_get_offsetof()
2329 return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel); in fiji_get_offsetof()
2374 smu_data->smc_state_table.UvdBootLevel = 0; in fiji_update_uvd_smc_table()
2376 smu_data->smc_state_table.UvdBootLevel = in fiji_update_uvd_smc_table()
2379 UvdBootLevel); in fiji_update_uvd_smc_table()
2385 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in fiji_update_uvd_smc_table()
2395 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in fiji_update_uvd_smc_table()
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| H A D | tonga_smumgr.c | 1321 table->UvdBootLevel = 0; in tonga_populate_smc_uvd_level()
2637 case UvdBootLevel: in tonga_get_offsetof()
2638 return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); in tonga_get_offsetof()
2683 smu_data->smc_state_table.UvdBootLevel = 0; in tonga_update_uvd_smc_table()
2685 smu_data->smc_state_table.UvdBootLevel = in tonga_update_uvd_smc_table()
2688 offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); in tonga_update_uvd_smc_table()
2694 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in tonga_update_uvd_smc_table()
2705 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in tonga_update_uvd_smc_table()
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| H A D | polaris10_smumgr.c | 1407 table->UvdBootLevel = 0; in polaris10_populate_smc_uvd_level()
2188 smu_data->smc_state_table.UvdBootLevel = 0; in polaris10_update_uvd_smc_table()
2190 smu_data->smc_state_table.UvdBootLevel = in polaris10_update_uvd_smc_table()
2193 UvdBootLevel); in polaris10_update_uvd_smc_table()
2199 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in polaris10_update_uvd_smc_table()
2209 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in polaris10_update_uvd_smc_table()
2350 case UvdBootLevel: in polaris10_get_offsetof()
2351 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); in polaris10_get_offsetof()
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| H A D | ci_smumgr.c | 2011 table->UvdBootLevel = 0; in ci_init_smc_table()
2870 smu_data->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_smc_table()
2872 smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1; in ci_update_uvd_smc_table()
2875 UvdBootLevel, smu_data->smc_state_table.UvdBootLevel); in ci_update_uvd_smc_table()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | vegam_smumgr.c | 337 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()
339 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table()
342 UvdBootLevel); in vegam_update_uvd_smc_table()
348 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in vegam_update_uvd_smc_table()
358 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in vegam_update_uvd_smc_table()
1321 table->UvdBootLevel = 0; in vegam_populate_smc_uvd_level()
2186 case UvdBootLevel: in vegam_get_offsetof()
2187 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel); in vegam_get_offsetof()
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| H A D | fiji_smumgr.c | 1565 table->UvdBootLevel = 0; in fiji_populate_smc_uvd_level()
2326 case UvdBootLevel: in fiji_get_offsetof()
2327 return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel); in fiji_get_offsetof()
2372 smu_data->smc_state_table.UvdBootLevel = 0; in fiji_update_uvd_smc_table()
2374 smu_data->smc_state_table.UvdBootLevel = in fiji_update_uvd_smc_table()
2377 UvdBootLevel); in fiji_update_uvd_smc_table()
2383 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in fiji_update_uvd_smc_table()
2393 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in fiji_update_uvd_smc_table()
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| H A D | tonga_smumgr.c | 1321 table->UvdBootLevel = 0; in tonga_populate_smc_uvd_level()
2637 case UvdBootLevel: in tonga_get_offsetof()
2638 return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); in tonga_get_offsetof()
2683 smu_data->smc_state_table.UvdBootLevel = 0; in tonga_update_uvd_smc_table()
2685 smu_data->smc_state_table.UvdBootLevel = in tonga_update_uvd_smc_table()
2688 offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); in tonga_update_uvd_smc_table()
2694 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in tonga_update_uvd_smc_table()
2705 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in tonga_update_uvd_smc_table()
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| H A D | polaris10_smumgr.c | 1534 table->UvdBootLevel = 0; in polaris10_populate_smc_uvd_level()
2288 smu_data->smc_state_table.UvdBootLevel = 0; in polaris10_update_uvd_smc_table()
2290 smu_data->smc_state_table.UvdBootLevel = in polaris10_update_uvd_smc_table()
2293 UvdBootLevel); in polaris10_update_uvd_smc_table()
2299 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in polaris10_update_uvd_smc_table()
2309 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in polaris10_update_uvd_smc_table()
2451 case UvdBootLevel: in polaris10_get_offsetof()
2452 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); in polaris10_get_offsetof()
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| H A D | ci_smumgr.c | 2012 table->UvdBootLevel = 0; in ci_init_smc_table()
2871 smu_data->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_smc_table()
2873 smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1; in ci_update_uvd_smc_table()
2876 UvdBootLevel, smu_data->smc_state_table.UvdBootLevel); in ci_update_uvd_smc_table()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | smu7_fusion.h | 240 uint8_t UvdBootLevel; member
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| H A D | smu7_discrete.h | 336 uint8_t UvdBootLevel; member
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | smu7_fusion.h | 240 uint8_t UvdBootLevel; member
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| H A D | smu7_discrete.h | 336 uint8_t UvdBootLevel; member
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