| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si.c | 1693 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1702 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1729 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
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| H A D | sid.h | 129 # define UPLL_RESET_MASK 0x00000001 macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | rv770.c | 85 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
96 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
114 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
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| H A D | rv770d.h | 43 # define UPLL_RESET_MASK 0x00000001 macro
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| H A D | r600.c | 215 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); in r600_set_uvd_clocks()
248 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
272 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
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| H A D | evergreen.c | 1226 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1235 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1260 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
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| H A D | si.c | 7036 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7045 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7070 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
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| H A D | sid.h | 128 # define UPLL_RESET_MASK 0x00000001 macro
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| H A D | evergreend.h | 349 # define UPLL_RESET_MASK 0x00000001 macro
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| H A D | r600d.h | 1557 # define UPLL_RESET_MASK 0x00000001 macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si.c | 1809 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1818 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1845 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
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| H A D | sid.h | 129 # define UPLL_RESET_MASK 0x00000001 macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | rv770.c | 88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
99 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
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| H A D | rv770d.h | 43 # define UPLL_RESET_MASK 0x00000001 macro
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| H A D | r600.c | 215 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); in r600_set_uvd_clocks()
248 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
272 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
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| H A D | si.c | 7028 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7037 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7062 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
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| H A D | evergreen.c | 1222 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1231 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1256 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
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| H A D | sid.h | 128 # define UPLL_RESET_MASK 0x00000001 macro
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| H A D | evergreend.h | 349 # define UPLL_RESET_MASK 0x00000001 macro
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| H A D | r600d.h | 1557 # define UPLL_RESET_MASK 0x00000001 macro
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