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Searched refs:UIC_ARG_MIB_SEL (Results 1 - 15 of 15) sorted by relevance

/kernel/linux/linux-5.10/drivers/scsi/ufs/
H A Dtc-dwc-g210.c34 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
36 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
38 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14, in tc_dwc_g210_setup_40bit_rmmi()
40 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6, in tc_dwc_g210_setup_40bit_rmmi()
42 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
44 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
46 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4, in tc_dwc_g210_setup_40bit_rmmi()
48 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
52 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
54 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG in tc_dwc_g210_setup_40bit_rmmi()
[all...]
H A Dufs-hisi.c31 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
34 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
48 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
51 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
146 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
148 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); in ufs_hisi_link_startup_pre_change()
150 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
152 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); in ufs_hisi_link_startup_pre_change()
154 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
158 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL( in ufs_hisi_link_startup_pre_change()
[all...]
H A Dufs-exynos.c159 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
161 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
162 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
168 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); in exynos7_ufs_pre_link()
188 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
189 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
190 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
419 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
421 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
423 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_0 in exynos_ufs_config_phy_time_attr()
[all...]
H A Dufshci.h235 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ macro
237 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
H A Dufs-qcom.c208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
H A Dufs-mediatek.c649 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0), in ufs_mtk_unipro_set_pm()
H A Dufshcd.c3896 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); in ufshcd_uic_change_pwr_mode()
4447 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
4452 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
7303 UIC_ARG_MIB_SEL( in ufshcd_tune_pa_tactivate()
7339 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()
7346 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()
/kernel/linux/linux-6.6/drivers/ufs/host/
H A Dtc-dwc-g210.c35 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
37 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
39 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14, in tc_dwc_g210_setup_40bit_rmmi()
41 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6, in tc_dwc_g210_setup_40bit_rmmi()
43 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
45 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
47 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4, in tc_dwc_g210_setup_40bit_rmmi()
49 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
53 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
55 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG in tc_dwc_g210_setup_40bit_rmmi()
[all...]
H A Dufs-hisi.c33 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
36 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
50 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
53 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
148 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
150 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); in ufs_hisi_link_startup_pre_change()
152 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
154 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); in ufs_hisi_link_startup_pre_change()
156 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
160 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL( in ufs_hisi_link_startup_pre_change()
[all...]
H A Dufs-exynos.c237 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in exynosauto_ufs_pre_link()
239 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in exynosauto_ufs_pre_link()
241 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in exynosauto_ufs_pre_link()
243 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in exynosauto_ufs_pre_link()
245 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in exynosauto_ufs_pre_link()
248 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); in exynosauto_ufs_pre_link()
249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in exynosauto_ufs_pre_link()
250 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in exynosauto_ufs_pre_link()
254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in exynosauto_ufs_pre_link()
257 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_E in exynosauto_ufs_pre_link()
[all...]
H A Dufs-sprd.c282 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL, in ufs_sprd_n6_phy_init()
284 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL, in ufs_sprd_n6_phy_init()
H A Dufs-qcom.c330 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
346 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
H A Dufs-mediatek.c1077 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0), in ufs_mtk_unipro_set_lpm()
/kernel/linux/linux-6.6/include/ufs/
H A Dufshci.h303 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ macro
305 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
/kernel/linux/linux-6.6/drivers/ufs/core/
H A Dufshcd.c4211 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); in ufshcd_uic_change_pwr_mode()
4783 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
4788 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
8188 UIC_ARG_MIB_SEL( in ufshcd_tune_pa_tactivate()
8224 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()
8231 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()

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