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Searched refs:TB_CFG_PORT (Results 1 - 24 of 24) sorted by relevance

/kernel/linux/linux-6.6/drivers/thunderbolt/
H A Dusb4.c188 if (tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_check_wakes()
218 if (tb_port_read(port, &val, TB_CFG_PORT, in link_is_usb4()
396 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); in usb4_switch_lane_bonding_possible()
431 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
454 ret = tb_port_write(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
1088 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
1093 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
1108 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
1113 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
1124 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_port_set_configured()
[all...]
H A Dclx.c43 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_pm_secondary_set()
53 return tb_port_write(port, &phy, TB_CFG_PORT, in tb_port_pm_secondary_set()
95 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_clx_supported()
118 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_clx_set()
128 return tb_port_write(port, &phy, TB_CFG_PORT, in tb_port_clx_set()
150 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_clx()
H A Dcap.c58 tb_port_read(port, &dummy, TB_CFG_PORT, 0, 1); in tb_port_dummy_read()
80 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in tb_port_next_cap()
99 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in __tb_port_find_cap()
H A Dtmu.c172 ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1); in tb_port_tmu_write()
179 return tb_port_write(port, &data, TB_CFG_PORT, in tb_port_tmu_write()
210 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_is_unidirectional()
223 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_is_enhanced()
240 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_enhanced_enable()
250 return tb_port_write(port, &val, TB_CFG_PORT, in tb_port_tmu_enhanced_enable()
265 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
275 ret = tb_port_write(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
280 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
290 return tb_port_write(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
[all...]
H A Dswitch.c476 res = tb_port_read(port, &phy, TB_CFG_PORT, port->cap_phy, 2); in tb_port_state()
593 TB_CFG_PORT, ADP_CS_4, 1); in tb_port_add_nfc_credits()
636 ret = tb_port_read(port, &phy, TB_CFG_PORT, in __tb_port_enable()
647 ret = tb_port_write(port, &phy, TB_CFG_PORT, in __tb_port_enable()
697 res = tb_port_read(port, &port->config, TB_CFG_PORT, 0, 8); in tb_init_port()
899 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_speed()
932 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_width()
951 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_is_width_supported()
985 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_set_link_width()
1007 return tb_port_write(port, &val, TB_CFG_PORT, in tb_port_set_link_width()
[all...]
H A Dtunnel.c396 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
403 ret = tb_port_write(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
409 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
599 ret = tb_port_read(in, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
604 ret = tb_port_read(out, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
610 ret = tb_port_write(out, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
668 return tb_port_write(in, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
696 ret = tb_port_read(in, &in_dp_cap, TB_CFG_PORT, in tb_dp_bandwidth_alloc_mode_enable()
701 ret = tb_port_read(out, &out_dp_cap, TB_CFG_PORT, in tb_dp_bandwidth_alloc_mode_enable()
864 ret = tb_port_read(in, &cap, TB_CFG_PORT, in tb_dp_bandwidth_mode_maximum_bandwidth()
[all...]
H A Ddma_port.c96 .space = TB_CFG_PORT, in dma_port_read()
137 .space = TB_CFG_PORT, in dma_port_write()
H A Dicm.c1864 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1867 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1881 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1886 ret = pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
1893 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1896 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1901 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1906 return pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
H A Ddebugfs.c153 ret = tb_port_write(port, &val, TB_CFG_PORT, offset, 1); in regs_write()
1103 ret = tb_port_read(port, &data, TB_CFG_PORT, cap + offset + i, 1); in cap_show_by_dw()
1127 ret = tb_port_read(port, data, TB_CFG_PORT, cap + offset, in cap_show()
1155 ret = tb_port_read(port, &header, TB_CFG_PORT, cap, 1); in port_cap_show()
1202 ret = tb_port_read(port, (u32 *)&header + 1, TB_CFG_PORT, in port_cap_show()
1246 ret = tb_port_read(port, data, TB_CFG_PORT, 0, ARRAY_SIZE(data)); in port_basic_regs_show()
H A Dtb_msgs.h17 TB_CFG_PORT = 1, enumerator
H A Deeprom.c381 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1); in tb_drom_parse_entry_port()
H A Dctl.c910 * @port: Port number when reading from %TB_CFG_PORT, %0 otherwise
981 * @port: Port number when writing to %TB_CFG_PORT, %0 otherwise
1056 if (space == TB_CFG_PORT && in tb_cfg_get_error()
H A Dxdomain.c549 ret = tb_port_read(port, val, TB_CFG_PORT, in tb_xdp_link_state_status_response()
1297 ret = tb_port_read(port, &val, TB_CFG_PORT, port->cap_phy + LANE_ADP_CS_1, 1); in tb_xdomain_link_state_change()
/kernel/linux/linux-5.10/drivers/thunderbolt/
H A Dusb4.c225 if (tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_check_wakes()
247 if (tb_port_read(port, &val, TB_CFG_PORT, in link_is_usb4()
398 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); in usb4_switch_lane_bonding_possible()
432 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
446 ret = tb_port_write(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
849 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
854 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
869 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
874 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
885 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_port_set_configured()
[all...]
H A Dcap.c58 tb_port_read(port, &dummy, TB_CFG_PORT, 0, 1); in tb_port_dummy_read()
80 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in tb_port_next_cap()
99 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in __tb_port_find_cap()
H A Dswitch.c519 res = tb_port_read(port, &phy, TB_CFG_PORT, port->cap_phy, 2); in tb_port_state()
621 TB_CFG_PORT, ADP_CS_4, 1); in tb_port_add_nfc_credits()
636 ret = tb_port_read(port, &data, TB_CFG_PORT, ADP_CS_5, 1); in tb_port_set_initial_credits()
643 return tb_port_write(port, &data, TB_CFG_PORT, ADP_CS_5, 1); in tb_port_set_initial_credits()
684 ret = tb_port_read(port, &phy, TB_CFG_PORT, in __tb_port_enable()
694 return tb_port_write(port, &phy, TB_CFG_PORT, in __tb_port_enable()
733 res = tb_port_read(port, &port->config, TB_CFG_PORT, 0, 8); in tb_init_port()
919 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_speed()
937 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_width()
954 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_is_width_supported()
[all...]
H A Dtmu.c90 ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1); in tb_port_tmu_write()
97 return tb_port_write(port, &data, TB_CFG_PORT, in tb_port_tmu_write()
123 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_is_unidirectional()
H A Ddebugfs.c149 ret = tb_port_write(port, &val, TB_CFG_PORT, offset, 1); in regs_write()
265 ret = tb_port_read(port, data, TB_CFG_PORT, cap + offset, in cap_show()
296 ret = tb_port_read(port, &header, TB_CFG_PORT, cap, 1); in port_cap_show()
332 ret = tb_port_read(port, (u32 *)&header + 1, TB_CFG_PORT, in port_cap_show()
385 ret = tb_port_read(port, data, TB_CFG_PORT, 0, ARRAY_SIZE(data)); in port_basic_regs_show()
H A Dtunnel.c269 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
276 ret = tb_port_write(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
282 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
444 ret = tb_port_read(in, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
449 ret = tb_port_read(out, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
455 ret = tb_port_write(out, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
503 return tb_port_write(in, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
560 ret = tb_port_read(in, &val, TB_CFG_PORT, in tb_dp_consumed_bandwidth()
580 ret = tb_port_read(in, &val, TB_CFG_PORT, in tb_dp_consumed_bandwidth()
H A Dicm.c1812 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1815 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1829 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1834 ret = pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
1841 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1844 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1849 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1854 return pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
H A Ddma_port.c96 .space = TB_CFG_PORT, in dma_port_read()
137 .space = TB_CFG_PORT, in dma_port_write()
H A Deeprom.c356 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1); in tb_drom_parse_entry_port()
H A Dtb_msgs.h17 TB_CFG_PORT = 1, enumerator
H A Dctl.c957 if (space == TB_CFG_PORT && in tb_cfg_get_error()

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