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Searched refs:SWD_CLK_DIV_CTRL_SEL (Results 1 - 5 of 5) sorted by relevance

/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dclock.c419 /* protect SWD_CLK_DIV_CTRL_SEL register from concurrent access via clk_enable/disable() */ in omap1_set_ext_clk_rate()
549 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
570 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
594 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_disable_generic()
615 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_disable_generic()
H A Dclock.h173 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
175 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 macro
H A Dclock_data.c536 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
H A Dclock.h270 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
272 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 macro
H A Dclock_data.c595 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),

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