| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_top.c | 115 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; in dpu_hw_get_danger_status()
227 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; in dpu_hw_get_safe_status()
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| H A D | dpu_hw_mdss.h | 108 SSPP_VIG2, enumerator
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| H A D | dpu_hw_ctl.c | 171 case SSPP_VIG2: in dpu_hw_ctl_update_pending_flush_sspp()
427 [SSPP_VIG2] = { { 0, 6, 4 }, { 3, 8 } },
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_cfg.c | 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
196 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
433 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
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| H A D | mdp5_ctl.c | 292 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
315 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask()
443 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()
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| H A D | mdp5_kms.c | 727 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init()
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| H A D | mdp5.xml.h | 71 SSPP_VIG2 = 3, enumerator
541 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); in __offset_PIPE()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_ctl.c | 294 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
317 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask()
445 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()
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| H A D | mdp5_cfg.c | 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
198 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
287 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
539 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
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| H A D | mdp5_kms.c | 688 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init()
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| H A D | mdp5.xml.h | 78 SSPP_VIG2 = 3, enumerator
552 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); in __offset_PIPE()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_ctl.c | 147 case SSPP_VIG2: in dpu_hw_ctl_get_bitmask_sspp()
403 case SSPP_VIG2: in dpu_hw_ctl_setup_blendstage()
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| H A D | dpu_hw_top.c | 140 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; in dpu_hw_get_danger_status()
237 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; in dpu_hw_get_safe_status()
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| H A D | dpu_hw_mdss.h | 111 SSPP_VIG2, enumerator
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| H A D | dpu_hw_interrupts.c | 386 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2},
387 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
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| H A D | dpu_hw_catalog.c | 346 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
| H A D | dpu_3_0_msm8998.h | 86 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_7_0_sm8350.h | 92 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_6_0_sm8250.h | 92 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_5_1_sc8180x.h | 92 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_8_0_sc8280xp.h | 92 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_8_1_sm8450.h | 93 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_9_0_sm8550.h | 94 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_5_0_sm8150.h | 93 .name = "sspp_2", .id = SSPP_VIG2,
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| H A D | dpu_4_0_sdm845.h | 84 .name = "sspp_2", .id = SSPP_VIG2,
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