| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_cfg.c | 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
195 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
432 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
641 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
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| H A D | mdp5_ctl.c | 291 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
314 case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3; in mdp_ctl_blend_ext_mask()
442 case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1; in mdp_ctl_flush_mask_pipe()
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| H A D | mdp5_kms.c | 727 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init()
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| H A D | mdp5.xml.h | 70 SSPP_VIG1 = 2, enumerator
540 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); in __offset_PIPE()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_top.c | 114 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; in dpu_hw_get_danger_status()
226 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; in dpu_hw_get_safe_status()
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| H A D | dpu_hw_mdss.h | 107 SSPP_VIG1, enumerator
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| H A D | dpu_hw_ctl.c | 168 case SSPP_VIG1: in dpu_hw_ctl_update_pending_flush_sspp()
426 [SSPP_VIG1] = { { 0, 3, 2 }, { 3, 4 } },
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_ctl.c | 293 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
316 case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3; in mdp_ctl_blend_ext_mask()
444 case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1; in mdp_ctl_flush_mask_pipe()
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| H A D | mdp5_cfg.c | 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
198 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
286 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
538 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
757 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
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| H A D | mdp5_kms.c | 688 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init()
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| H A D | mdp5.xml.h | 77 SSPP_VIG1 = 2, enumerator
551 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); in __offset_PIPE()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_ctl.c | 144 case SSPP_VIG1: in dpu_hw_ctl_get_bitmask_sspp()
395 case SSPP_VIG1: in dpu_hw_ctl_setup_blendstage()
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| H A D | dpu_hw_top.c | 139 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; in dpu_hw_get_danger_status()
236 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; in dpu_hw_get_safe_status()
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| H A D | dpu_hw_mdss.h | 110 SSPP_VIG1, enumerator
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| H A D | dpu_hw_interrupts.c | 380 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
381 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
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| H A D | dpu_hw_catalog.c | 344 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
| H A D | dpu_3_0_msm8998.h | 78 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_7_0_sm8350.h | 84 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_6_0_sm8250.h | 84 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_5_1_sc8180x.h | 84 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_8_0_sc8280xp.h | 84 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_8_1_sm8450.h | 85 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_9_0_sm8550.h | 86 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_5_0_sm8150.h | 85 .name = "sspp_1", .id = SSPP_VIG1,
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| H A D | dpu_4_0_sdm845.h | 76 .name = "sspp_1", .id = SSPP_VIG1,
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