| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_cfg.c | 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
195 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
290 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
357 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
432 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
641 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
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| H A D | mdp5_ctl.c | 290 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage); in mdp_ctl_blend_mask()
313 case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3; in mdp_ctl_blend_ext_mask()
441 case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0; in mdp_ctl_flush_mask_pipe()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_cfg.c | 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
117 [SSPP_VIG0] = 1,
198 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
286 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
386 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
458 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
538 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
757 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
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| H A D | mdp5_ctl.c | 292 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage); in mdp_ctl_blend_mask()
315 case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3; in mdp_ctl_blend_ext_mask()
443 case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0; in mdp_ctl_flush_mask_pipe()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_top.c | 113 status->sspp[SSPP_VIG0] = (value >> 4) & 0x3; in dpu_hw_get_danger_status()
225 status->sspp[SSPP_VIG0] = (value >> 4) & 0x1; in dpu_hw_get_safe_status()
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| H A D | dpu_plane.c | 239 pipe->sspp->idx - SSPP_VIG0, in _dpu_plane_calc_fill_level()
283 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
287 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, in _dpu_plane_set_qos_lut()
292 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
296 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
303 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
328 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_ctrl()
382 qos_params.num = pipe->sspp->idx - SSPP_VIG0; in _dpu_plane_set_qos_remap()
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| H A D | dpu_hw_mdss.h | 106 SSPP_VIG0, enumerator
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| H A D | dpu_hw_ctl.c | 165 case SSPP_VIG0: in dpu_hw_ctl_update_pending_flush_sspp()
425 [SSPP_VIG0] = { { 0, 0, 0 }, { 3, 0 } },
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
| H A D | dpu_6_3_sm6115.h | 40 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_6_5_qcm2290.h | 39 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_6_9_sm6375.h | 41 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_6_2_sc7180.h | 53 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_6_4_sm6350.h | 60 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_5_4_sm6125.h | 69 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_7_2_sc7280.h | 58 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_3_0_msm8998.h | 70 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_7_0_sm8350.h | 76 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_6_0_sm8250.h | 76 .name = "sspp_0", .id = SSPP_VIG0,
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| H A D | dpu_5_1_sc8180x.h | 76 .name = "sspp_0", .id = SSPP_VIG0,
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_plane.c | 270 plane->base.id, pdpu->pipe - SSPP_VIG0, in _dpu_plane_calc_fill_level()
335 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
341 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_lut()
386 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_danger_lut()
394 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_danger_lut()
438 pdpu->pipe - SSPP_VIG0, in _dpu_plane_set_qos_ctrl()
489 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; in _dpu_plane_set_qos_remap()
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| H A D | dpu_hw_ctl.c | 141 case SSPP_VIG0: in dpu_hw_ctl_get_bitmask_sspp()
387 case SSPP_VIG0: in dpu_hw_ctl_setup_blendstage()
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| H A D | dpu_hw_top.c | 138 status->sspp[SSPP_VIG0] = (value >> 4) & 0x3; in dpu_hw_get_danger_status()
235 status->sspp[SSPP_VIG0] = (value >> 4) & 0x1; in dpu_hw_get_safe_status()
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| H A D | dpu_hw_mdss.h | 109 SSPP_VIG0, enumerator
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| H A D | dpu_hw_interrupts.c | 374 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
375 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
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| H A D | dpu_hw_catalog.c | 342 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
364 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
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