| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 47 #define SRC_MASK_FSYS 0x10340 macro
173 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
175 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
177 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
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| H A D | clk-exynos5250.c | 54 #define SRC_MASK_FSYS 0x10340 macro
135 SRC_MASK_FSYS,
476 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
478 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
480 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
482 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
484 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
486 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
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| H A D | clk-exynos4.c | 62 #define SRC_MASK_FSYS 0xc340 macro
211 SRC_MASK_FSYS,
268 { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
767 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
769 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
771 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
773 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
775 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
940 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
982 SRC_MASK_FSYS, 2
[all...] |
| H A D | clk-exynos3250.c | 47 #define SRC_MASK_FSYS 0xc340 macro
131 SRC_MASK_FSYS,
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| H A D | clk-exynos5420.c | 78 #define SRC_MASK_FSYS 0x10340 macro
202 SRC_MASK_FSYS,
282 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
1048 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
|
| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 47 #define SRC_MASK_FSYS 0x10340 macro
176 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
178 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
180 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
|
| H A D | clk-exynos5250.c | 54 #define SRC_MASK_FSYS 0x10340 macro
138 SRC_MASK_FSYS,
479 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
481 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
483 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
485 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
487 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
489 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
|
| H A D | clk-exynos4.c | 62 #define SRC_MASK_FSYS 0xc340 macro
215 SRC_MASK_FSYS,
272 { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
771 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
773 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
775 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
777 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
779 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
944 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
986 SRC_MASK_FSYS, 2
[all...] |
| H A D | clk-exynos3250.c | 47 #define SRC_MASK_FSYS 0xc340 macro
136 SRC_MASK_FSYS,
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| H A D | clk-exynos5420.c | 78 #define SRC_MASK_FSYS 0x10340 macro
205 SRC_MASK_FSYS,
285 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
1051 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
|