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Searched refs:SOC15_REG_ENTRY_OFFSET (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15.h84 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) macro
H A Dgfx_v9_4.c887 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_count()
922 RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_reset_ras_error_count()
1013 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_status()
H A Dmmhub_v1_0.c758 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_query_ras_error_count()
776 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_reset_ras_error_count()
H A Dmmhub_v9_4.c1606 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_query_ras_error_count()
1623 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_reset_ras_error_count()
1648 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i])); in mmhub_v9_4_query_ras_error_status()
H A Dgfx_v9_0.c4579 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) in gfx_v9_0_do_edc_gpr_workarounds()
4607 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()
4635 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()
6615 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_reset_ras_error_count()
6678 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_query_ras_error_count()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c382 ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i]) in gfx_v9_4_2_run_shader()
1512 WREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()
1517 data = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()
1528 WREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()
1615 WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j); in gfx_v9_4_2_query_utc_edc_count()
1619 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), in gfx_v9_4_2_query_utc_edc_count()
1624 data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg)); in gfx_v9_4_2_query_utc_edc_count()
1634 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), in gfx_v9_4_2_query_utc_edc_count()
1686 value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_reset_ea_err_status()
1689 WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_reg in gfx_v9_4_2_reset_ea_err_status()
[all...]
H A Dsoc15.h91 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) macro
H A Dmmhub_v1_7.c1256 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i])); in mmhub_v1_7_query_ras_error_count()
1273 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0); in mmhub_v1_7_reset_ras_error_count()
1296 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i])); in mmhub_v1_7_query_ras_error_status()
1315 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in mmhub_v1_7_reset_ras_error_status()
1319 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]), in mmhub_v1_7_reset_ras_error_status()
H A Dgfx_v9_4.c887 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_count()
921 RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_reset_ras_error_count()
990 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_status()
H A Dmmhub_v1_0.c758 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_query_ras_error_count()
776 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_reset_ras_error_count()
H A Dmmhub_v9_4.c1611 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_query_ras_error_count()
1628 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_reset_ras_error_count()
1653 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i])); in mmhub_v9_4_query_ras_error_status()
H A Dgfx_v9_0.c4413 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) in gfx_v9_0_do_edc_gpr_workarounds()
4441 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()
4469 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()
6688 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_reset_ras_error_count()
6751 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_query_ras_error_count()

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