SIMM (reference) in projects: kernel - OpenGrok search results

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Searched refs:SIMM (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/arch/mips/mm/
H A D	uasm-mips.c	51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 68 [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 76 [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 120 [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 121 [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 122 [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 126 [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 127 [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 129 [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 130 [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, [all...]
H A D	uasm-micromips.c	44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT \| RS \| SIMM}, 80 [insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 82 [insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 83 [insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS \| RT \| SIMM}, 85 [insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS \| SIMM}, 86 [insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 96 [insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT \| RS \| SIMM}, 98 [insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT \| RS \| SIMM}, 104 [insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, [all...]
H A D	uasm.c	`21 SIMM = 0x010, enumerator`
/kernel/linux/linux-6.6/arch/mips/mm/
H A D	uasm-mips.c	51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 68 [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 76 [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 120 [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 121 [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 122 [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 126 [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 127 [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 129 [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, 130 [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM}, [all...]
H A D	uasm-micromips.c	44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT \| RS \| SIMM}, 80 [insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 82 [insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 83 [insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS \| RT \| SIMM}, 85 [insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS \| SIMM}, 86 [insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, 96 [insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT \| RS \| SIMM}, 98 [insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT \| RS \| SIMM}, 104 [insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT \| RS \| SIMM}, [all...]
H A D	uasm.c	`21 SIMM = 0x010, enumerator`
/kernel/linux/linux-5.10/arch/powerpc/xmon/
H A D	ppc-opc.c	`747 /* The SIMM field in a VX form instruction, and TE in Z form. */ 748 #define SIMM VD + 1 749 #define TE SIMM 753 #define UIMM SIMM + 1 3309 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3311 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3446 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3488 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3504 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 746 #define SIMM global() macro`
/kernel/linux/linux-6.6/arch/powerpc/xmon/
H A D	ppc-opc.c	`747 /* The SIMM field in a VX form instruction, and TE in Z form. */ 748 #define SIMM VD + 1 749 #define TE SIMM 753 #define UIMM SIMM + 1 3309 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3311 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3446 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3488 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3504 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 746 #define SIMM global() macro`

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