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Searched refs:SDMA_PKT_WRITE_UNTILED_DW_3_COUNT (Results 1 - 21 of 21) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v2_4.c570 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); in sdma_v2_4_ring_test_ring()
624 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); in sdma_v2_4_ring_test_ib()
H A Dsdma_v5_2.c877 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v5_2_ring_test_ring()
937 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_2_ring_test_ib()
H A Dsdma_v5_0.c940 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v5_0_ring_test_ring()
1001 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_0_ring_test_ib()
H A Dsdma_v3_0.c842 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); in sdma_v3_0_ring_test_ring()
896 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); in sdma_v3_0_ring_test_ib()
H A Dsdma_v4_0.c1553 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v4_0_ring_test_ring()
1607 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v4_0_ring_test_ib()
H A Diceland_sdma_pkt_open.h1386 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
H A Dtonga_sdma_pkt_open.h1386 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
H A Dvega10_sdma_pkt_open.h1590 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
H A Dnavi10_sdma_pkt_open.h2707 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v3_0.c832 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); in sdma_v3_0_ring_test_ring()
887 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); in sdma_v3_0_ring_test_ib()
H A Dsdma_v2_4.c560 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); in sdma_v2_4_ring_test_ring()
615 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); in sdma_v2_4_ring_test_ib()
H A Dsdma_v4_4_2.c983 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v4_4_2_ring_test_ring()
1038 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v4_4_2_ring_test_ib()
H A Dsdma_v5_0.c1027 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v5_0_ring_test_ring()
1109 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_0_ring_test_ib()
H A Dsdma_v5_2.c863 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v5_2_ring_test_ring()
944 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_2_ring_test_ib()
H A Dsdma_v6_0.c914 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v6_0_ring_test_ring()
995 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v6_0_ring_test_ib()
H A Dsdma_v4_0.c1448 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v4_0_ring_test_ring()
1503 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v4_0_ring_test_ib()
H A Diceland_sdma_pkt_open.h1386 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
H A Dtonga_sdma_pkt_open.h1386 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
H A Dvega10_sdma_pkt_open.h1590 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
H A Dnavi10_sdma_pkt_open.h2707 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro
H A Dsdma_v6_0_0_pkt_open.h3113 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) macro

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