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Searched refs:SDMA_PKT_POLL_REGMEM_DW5_INTERVAL (Results 1 - 21 of 21) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v2_4.c295 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_hdp_flush()
785 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_pipeline_sync()
811 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_vm_flush()
H A Dsdma_v5_2.c403 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_hdp_flush()
1106 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_pipeline_sync()
1145 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_2_ring_emit_reg_wait()
H A Dsdma_v5_0.c469 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_hdp_flush()
1169 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_pipeline_sync()
1208 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_0_ring_emit_reg_wait()
H A Dsdma_v3_0.c469 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_hdp_flush()
1056 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_pipeline_sync()
1082 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_vm_flush()
H A Diceland_sdma_pkt_open.h2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
H A Dtonga_sdma_pkt_open.h2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
H A Dvega10_sdma_pkt_open.h2511 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
H A Dsdma_v4_0.c887 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_0_wait_reg_mem()
H A Dnavi10_sdma_pkt_open.h3835 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v3_0.c465 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_hdp_flush()
1048 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_pipeline_sync()
1075 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_vm_flush()
H A Dsdma_v2_4.c291 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_hdp_flush()
777 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_pipeline_sync()
804 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_vm_flush()
H A Dsdma_v5_0.c500 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_hdp_flush()
1283 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_pipeline_sync()
1323 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_0_ring_emit_reg_wait()
H A Dsdma_v5_2.c305 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_hdp_flush()
1119 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_pipeline_sync()
1159 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_2_ring_emit_reg_wait()
H A Dsdma_v6_0.c323 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_hdp_flush()
1168 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_pipeline_sync()
1228 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v6_0_ring_emit_reg_wait()
H A Diceland_sdma_pkt_open.h2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
H A Dsdma_v4_4_2.c352 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_4_2_wait_reg_mem()
H A Dtonga_sdma_pkt_open.h2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
H A Dsdma_v4_0.c801 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_0_wait_reg_mem()
H A Dvega10_sdma_pkt_open.h2511 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
H A Dnavi10_sdma_pkt_open.h3835 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro
H A Dsdma_v6_0_0_pkt_open.h4539 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) macro

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