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Searched refs:SCL (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-acorn.c19 #define SCL 0x02 macro
24 * Note also that we need to preserve the value of SCL and
32 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setscl()
36 ones |= SCL; in ioc_setscl()
38 ones &= ~SCL; in ioc_setscl()
47 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setsda()
62 return (ioc_readb(IOC_CONTROL) & SCL) != 0; in ioc_getscl()
87 force_ones = FORCE_ONES | SCL | SDA; in i2c_ioc_init()
H A Di2c-versatile.c20 #define SCL (1 << 0) macro
40 writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); in i2c_versatile_setscl()
52 return !!(readl(i2c->base + I2C_CONTROL) & SCL); in i2c_versatile_getscl()
79 writel(SCL | SDA, i2c->base + I2C_CONTROLS); in i2c_versatile_probe()
/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-acorn.c19 #define SCL 0x02 macro
24 * Note also that we need to preserve the value of SCL and
32 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setscl()
36 ones |= SCL; in ioc_setscl()
38 ones &= ~SCL; in ioc_setscl()
47 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setsda()
62 return (ioc_readb(IOC_CONTROL) & SCL) != 0; in ioc_getscl()
87 force_ones = FORCE_ONES | SCL | SDA; in i2c_ioc_init()
H A Di2c-versatile.c20 #define SCL (1 << 0) macro
40 writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); in i2c_versatile_setscl()
52 return !!(readl(i2c->base + I2C_CONTROL) & SCL); in i2c_versatile_getscl()
77 writel(SCL | SDA, i2c->base + I2C_CONTROLS); in i2c_versatile_probe()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_sw.c31 #define SCL false macro
87 if (read_bit_from_ddc(ddc, SCL)) in wait_for_scl_high_sw()
115 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
120 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
126 * after the SCL pulse we use to send our last data bit. in write_byte_sw()
136 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
147 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
166 * bit is read while SCL is high in read_byte_sw()
170 write_bit_to_ddc(ddc_handle, SCL, true); in read_byte_sw()
178 write_bit_to_ddc(ddc_handle, SCL, fals in read_byte_sw()
[all...]
H A Ddce_transform.h76 SRI(SCL_MODE, SCL, id), \
77 SRI(SCL_TAP_CONTROL, SCL, id), \
78 SRI(SCL_CONTROL, SCL, id), \
79 SRI(SCL_BYPASS_CONTROL, SCL, id), \
80 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
81 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
82 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
83 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
84 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
85 SRI(SCL_COEF_RAM_TAP_DATA, SCL, i
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_sw.c29 #define SCL false macro
85 if (read_bit_from_ddc(ddc, SCL)) in wait_for_scl_high_sw()
113 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
118 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
124 * after the SCL pulse we use to send our last data bit. in write_byte_sw()
134 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
145 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
164 * bit is read while SCL is high in read_byte_sw()
168 write_bit_to_ddc(ddc_handle, SCL, true); in read_byte_sw()
176 write_bit_to_ddc(ddc_handle, SCL, fals in read_byte_sw()
[all...]
H A Ddce_transform.h76 SRI(SCL_MODE, SCL, id), \
77 SRI(SCL_TAP_CONTROL, SCL, id), \
78 SRI(SCL_CONTROL, SCL, id), \
79 SRI(SCL_BYPASS_CONTROL, SCL, id), \
80 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
81 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
82 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
83 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
84 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
85 SRI(SCL_COEF_RAM_TAP_DATA, SCL, i
[all...]
/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-rs5c313.c73 #define SCL SCSPTR1_SPB0DT macro
94 /* And Initialize SCL for RS5C313 clock */ in rs5c313_init_port()
95 scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */ in rs5c313_init_port()
97 scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */ in rs5c313_init_port()
116 scsptr1_data &= ~SCL; /* SCL:L */ in rs5c313_write_data()
119 scsptr1_data |= SCL; /* SCL:H */ in rs5c313_write_data()
136 scsptr1_data &= ~SCL; /* SC in rs5c313_read_data()
[all...]
/kernel/linux/linux-6.6/drivers/rtc/
H A Drtc-rs5c313.c73 #define SCL SCSPTR1_SPB0DT macro
94 /* And Initialize SCL for RS5C313 clock */ in rs5c313_init_port()
95 scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */ in rs5c313_init_port()
97 scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */ in rs5c313_init_port()
116 scsptr1_data &= ~SCL; /* SCL:L */ in rs5c313_write_data()
119 scsptr1_data |= SCL; /* SCL:H */ in rs5c313_write_data()
136 scsptr1_data &= ~SCL; /* SC in rs5c313_read_data()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/
H A Dddc_regs.h171 DDC_I2C_REG_LIST(SCL)\
190 DDC_REG_LIST_DCN2(SCL)\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/
H A Dddc_regs.h178 DDC_I2C_REG_LIST(SCL)\
197 DDC_REG_LIST_DCN2(SCL)\
/kernel/linux/linux-5.10/drivers/scsi/
H A Dnsp32.c3228 nsp32_prom_set(data, SCL, 1); in nsp32_prom_start()
3231 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting in nsp32_prom_start()
3233 nsp32_prom_set(data, SCL, 0); in nsp32_prom_start()
3239 nsp32_prom_set(data, SCL, 1); in nsp32_prom_stop()
3243 nsp32_prom_set(data, SCL, 0); in nsp32_prom_stop()
3250 nsp32_prom_set(data, SCL, 1 ); in nsp32_prom_write_bit()
3251 nsp32_prom_set(data, SCL, 0 ); in nsp32_prom_write_bit()
3260 nsp32_prom_set(data, SCL, 1); in nsp32_prom_read_bit()
3264 nsp32_prom_set(data, SCL, 0); in nsp32_prom_read_bit()
H A Dnsp32.h392 # define SCL BIT(0) macro
/kernel/linux/linux-6.6/drivers/scsi/
H A Dnsp32.c3229 nsp32_prom_set(data, SCL, 1); in nsp32_prom_start()
3232 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting in nsp32_prom_start()
3234 nsp32_prom_set(data, SCL, 0); in nsp32_prom_start()
3240 nsp32_prom_set(data, SCL, 1); in nsp32_prom_stop()
3244 nsp32_prom_set(data, SCL, 0); in nsp32_prom_stop()
3251 nsp32_prom_set(data, SCL, 1 ); in nsp32_prom_write_bit()
3252 nsp32_prom_set(data, SCL, 0 ); in nsp32_prom_write_bit()
3261 nsp32_prom_set(data, SCL, 1); in nsp32_prom_read_bit()
3265 nsp32_prom_set(data, SCL, 0); in nsp32_prom_read_bit()
H A Dnsp32.h392 # define SCL BIT(0) macro

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