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Help
Searched
refs:S3C64XX_GPIOREG
(Results
1 - 4
of
4
) sorted by relevance
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
H
A
D
regs-gpio-s3c64xx.h
17
#define
S3C64XX_GPIOREG
(reg) (S3C64XX_VA_GPIO + (reg))
macro
19
#define S3C64XX_GPA_BASE
S3C64XX_GPIOREG
(0x0000)
20
#define S3C64XX_GPB_BASE
S3C64XX_GPIOREG
(0x0020)
21
#define S3C64XX_GPC_BASE
S3C64XX_GPIOREG
(0x0040)
22
#define S3C64XX_GPD_BASE
S3C64XX_GPIOREG
(0x0060)
23
#define S3C64XX_GPE_BASE
S3C64XX_GPIOREG
(0x0080)
24
#define S3C64XX_GPF_BASE
S3C64XX_GPIOREG
(0x00A0)
25
#define S3C64XX_GPG_BASE
S3C64XX_GPIOREG
(0x00C0)
26
#define S3C64XX_GPH_BASE
S3C64XX_GPIOREG
(0x00E0)
27
#define S3C64XX_GPI_BASE
S3C64XX_GPIOREG
(
[all...]
H
A
D
regs-gpio-memport-s3c64xx.h
14
#define S3C64XX_MEM0CONSTOP
S3C64XX_GPIOREG
(0x1B0)
15
#define S3C64XX_MEM1CONSTOP
S3C64XX_GPIOREG
(0x1B4)
17
#define S3C64XX_MEM0CONSLP0
S3C64XX_GPIOREG
(0x1C0)
18
#define S3C64XX_MEM0CONSLP1
S3C64XX_GPIOREG
(0x1C4)
19
#define S3C64XX_MEM1CONSLP
S3C64XX_GPIOREG
(0x1C8)
21
#define S3C64XX_MEM0DRVCON
S3C64XX_GPIOREG
(0x1D0)
22
#define S3C64XX_MEM1DRVCON
S3C64XX_GPIOREG
(0x1D4)
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
H
A
D
regs-gpio-s3c64xx.h
17
#define
S3C64XX_GPIOREG
(reg) (S3C64XX_VA_GPIO + (reg))
macro
19
#define S3C64XX_GPA_BASE
S3C64XX_GPIOREG
(0x0000)
20
#define S3C64XX_GPB_BASE
S3C64XX_GPIOREG
(0x0020)
21
#define S3C64XX_GPC_BASE
S3C64XX_GPIOREG
(0x0040)
22
#define S3C64XX_GPD_BASE
S3C64XX_GPIOREG
(0x0060)
23
#define S3C64XX_GPE_BASE
S3C64XX_GPIOREG
(0x0080)
24
#define S3C64XX_GPF_BASE
S3C64XX_GPIOREG
(0x00A0)
25
#define S3C64XX_GPG_BASE
S3C64XX_GPIOREG
(0x00C0)
26
#define S3C64XX_GPH_BASE
S3C64XX_GPIOREG
(0x00E0)
27
#define S3C64XX_GPI_BASE
S3C64XX_GPIOREG
(
[all...]
H
A
D
regs-gpio-memport-s3c64xx.h
14
#define S3C64XX_MEM0CONSTOP
S3C64XX_GPIOREG
(0x1B0)
15
#define S3C64XX_MEM1CONSTOP
S3C64XX_GPIOREG
(0x1B4)
17
#define S3C64XX_MEM0CONSLP0
S3C64XX_GPIOREG
(0x1C0)
18
#define S3C64XX_MEM0CONSLP1
S3C64XX_GPIOREG
(0x1C4)
19
#define S3C64XX_MEM1CONSLP
S3C64XX_GPIOREG
(0x1C8)
21
#define S3C64XX_MEM0DRVCON
S3C64XX_GPIOREG
(0x1D0)
22
#define S3C64XX_MEM1DRVCON
S3C64XX_GPIOREG
(0x1D4)
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