Searched refs:RY (Results 1 - 4 of 4) sorted by relevance
| /kernel/linux/linux-5.10/arch/x86/crypto/ |
| H A D | twofish-x86_64-asm_64-3way.S | 144 g1g2_3(ab, cd, s0, s1, s2, s3, s0, s1, s2, s3, RX, RY); \
151 g1g2_3(ba, dc, s1, s2, s3, s0, s3, s0, s1, s2, RY, RX); \
|
| /kernel/linux/linux-6.6/arch/x86/crypto/ |
| H A D | twofish-x86_64-asm_64-3way.S | 144 g1g2_3(ab, cd, s0, s1, s2, s3, s0, s1, s2, s3, RX, RY); \
151 g1g2_3(ba, dc, s1, s2, s3, s0, s3, s0, s1, s2, RY, RX); \
|
| /kernel/linux/linux-5.10/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 592 /* The RY field of the SE_RR form instruction. */
593 #define RY ARX + 1
594 #define RZ RY
598 #define ARY RY + 1
964 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
7006 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7007 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7009 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7010 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7011 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
591 #define RY global() macro
[all...] |
| /kernel/linux/linux-6.6/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 592 /* The RY field of the SE_RR form instruction. */
593 #define RY ARX + 1
594 #define RZ RY
598 #define ARY RY + 1
964 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
7006 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7007 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7009 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7010 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7011 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
591 #define RY global() macro
[all...] |
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