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Searched refs:RREG32_SOC15_NO_KIQ (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c84 *arg = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu_cmn_read_arg()
93 cur_value = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_cmn_wait_for_response()
104 return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO; in smu_cmn_wait_for_response()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h38 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ macro
H A Dgfx_v9_0.c4166 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4167 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4168 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4173 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h74 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ macro
H A Dgfx_v10_0.c7315 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7316 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7317 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7322 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7330 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); in gfx_v10_0_get_gpu_clock_counter()
7331 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); in gfx_v10_0_get_gpu_clock_counter()
7332 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); in gfx_v10_0_get_gpu_clock_counter()
7337 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); in gfx_v10_0_get_gpu_clock_counter()
7345 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); in gfx_v10_0_get_gpu_clock_counter()
7346 clock_lo = RREG32_SOC15_NO_KIQ(SMUI in gfx_v10_0_get_gpu_clock_counter()
[all...]
H A Dgfx_v9_0.c4000 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4001 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4002 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4007 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); in gfx_v9_0_get_gpu_clock_counter()

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