| /kernel/linux/linux-5.10/sound/hda/ |
| H A D | hdmi_chmap.c | 20 * RL RLC RC RRC RR
35 RRC = (1 << 9), /* Rear Right Center */ enumerator
52 /* 6 */ "RLC/RRC",
69 [6] = RLC | RRC,
90 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
137 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
147 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
148 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
149 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
403 { SNDRV_CHMAP_RRC, RRC },
[all...] |
| /kernel/linux/linux-6.6/sound/hda/ |
| H A D | hdmi_chmap.c | 20 * RL RLC RC RRC RR
35 RRC = (1 << 9), /* Rear Right Center */ enumerator
52 /* 6 */ "RLC/RRC",
69 [6] = RLC | RRC,
90 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
137 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
147 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
148 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
149 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
403 { SNDRV_CHMAP_RRC, RRC },
[all...] |
| /kernel/linux/linux-5.10/sound/x86/ |
| H A D | intel_hdmi_audio.h | 47 * RL RLC RC RRC RR
63 RRC = (1 << 9), /* Rear Right Center */ enumerator
|
| H A D | intel_hdmi_audio.c | 66 [6] = RLC | RRC,
95 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
105 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
106 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
107 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
130 { SNDRV_CHMAP_RRC, 0x07, RRC },
|
| /kernel/linux/linux-6.6/sound/x86/ |
| H A D | intel_hdmi_audio.h | 47 * RL RLC RC RRC RR
63 RRC = (1 << 9), /* Rear Right Center */ enumerator
|
| H A D | intel_hdmi_audio.c | 68 [6] = RLC | RRC,
97 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
107 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
108 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
109 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
132 { SNDRV_CHMAP_RRC, 0x07, RRC },
|
| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| H A D | hdmi-codec.c | 35 * RL RLC RC RRC RR
49 RRC = BIT(9), /* Rear Right Center */ enumerator
222 .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
241 .mask = FL | FR | RL | RR | RLC | RRC },
243 .mask = FL | FR | LFE | RL | RR | RLC | RRC },
245 .mask = FL | FR | FC | RL | RR | RLC | RRC },
317 [4] = RC, [5] = FLC | FRC, [6] = RLC | RRC, in hdmi_codec_spk_mask_from_alloc()
|
| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| H A D | hdmi-codec.c | 30 * RL RLC RC RRC RR
44 RRC = BIT(9), /* Rear Right Center */ enumerator
217 .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
236 .mask = FL | FR | RL | RR | RLC | RRC },
238 .mask = FL | FR | LFE | RL | RR | RLC | RRC },
240 .mask = FL | FR | FC | RL | RR | RLC | RRC },
314 [4] = RC, [5] = FLC | FRC, [6] = RLC | RRC, in hdmi_codec_spk_mask_from_alloc()
|
| /kernel/linux/linux-5.10/drivers/net/wan/ |
| H A D | hd64570.h | 72 #define RRC 0x1A /* RX Ready Control */ macro
|
| H A D | hd64572.h | 91 #define RRC 0x14a /* RX Ready control reg */ macro
|
| H A D | hd64570.c | 492 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/ in sca_open()
|
| /kernel/linux/linux-6.6/drivers/net/wan/ |
| H A D | hd64570.h | 72 #define RRC 0x1A /* RX Ready Control */ macro
|
| H A D | hd64572.h | 91 #define RRC 0x14a /* RX Ready control reg */ macro
|
| H A D | hd64570.c | 505 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/ in sca_open()
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/renesas/ |
| H A D | rswitch.c | 44 iowrite32(RRC_RR, priv->addr + RRC); in rswitch_reset()
45 iowrite32(RRC_RR_CLR, priv->addr + RRC); in rswitch_reset()
|
| H A D | rswitch.h | 447 RRC = CARO + 0x0004, enumerator
|
| /kernel/linux/linux-5.10/drivers/tty/ |
| H A D | synclinkmp.c | 335 #define RRC 0x3a macro
4442 /* RRC Receive Ready Control 0 in async_mode()
4445 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte in async_mode()
4447 write_reg(info, RRC, 0x00); in async_mode()
4619 /* RRC Receive Ready Control 0 in hdlc_mode()
4622 * 04..00 RRC<4..0> Rx FIFO trigger active in hdlc_mode()
4624 write_reg(info, RRC, rx_active_fifo_level); in hdlc_mode()
|