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Searched refs:REG_T1 (Results 1 - 9 of 9) sorted by relevance

/kernel/linux/linux-5.10/arch/loongarch/include/asm/
H A Dmodule.h61 addu16id = larch_insn_gen_addu16id(REG_T1, REG_ZERO, ADDR_IMM(val, ADDU16ID)); in emit_plt_entry()
62 lu32id = larch_insn_gen_lu32id(REG_T1, ADDR_IMM(val, LU32ID)); in emit_plt_entry()
63 lu52id = larch_insn_gen_lu52id(REG_T1, REG_T1, ADDR_IMM(val, LU52ID)); in emit_plt_entry()
64 jirl = larch_insn_gen_jirl(0, REG_T1, 0, (val & 0xffff)); in emit_plt_entry()
H A Dloongarchregs.h81 #define REG_T1 0xd macro
/kernel/linux/linux-5.10/arch/riscv/include/asm/
H A Dmodule.h61 #define REG_T1 0x6 macro
84 OPC_LD | (lo12 << 20) | (REG_T0 << 15) | (REG_T1 << 7), in emit_plt_entry()
85 OPC_JALR | (REG_T1 << 15) in emit_plt_entry()
/kernel/linux/linux-6.6/arch/riscv/include/asm/
H A Dmodule.h62 #define REG_T1 0x6 macro
85 OPC_LD | (lo12 << 20) | (REG_T0 << 15) | (REG_T1 << 7), in emit_plt_entry()
86 OPC_JALR | (REG_T1 << 15) in emit_plt_entry()
/kernel/linux/linux-5.10/arch/x86/crypto/
H A Dsha1_avx2_x86_64_asm.S92 #define REG_T1 %r11d define
117 .set T1, REG_T1
H A Dsha1_ssse3_asm.S39 #define REG_T1 %eax define
196 .set T1, REG_T1
/kernel/linux/linux-6.6/arch/x86/crypto/
H A Dsha1_avx2_x86_64_asm.S92 #define REG_T1 %r11d define
117 .set T1, REG_T1
H A Dsha1_ssse3_asm.S40 #define REG_T1 %eax define
197 .set T1, REG_T1
/kernel/linux/linux-6.6/arch/loongarch/include/asm/
H A Dloongarch.h36 #define REG_T1 0xd macro

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