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Searched refs:REG_SET_FIELD (Results 1 - 25 of 174) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v3_0_1.c81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v3_0_1_get_invalidate_req()
83 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v3_0_1_get_invalidate_req()
84 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v3_0_1_get_invalidate_req()
85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v3_0_1_get_invalidate_req()
86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v3_0_1_get_invalidate_req()
87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v3_0_1_get_invalidate_req()
88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v3_0_1_get_invalidate_req()
89 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v3_0_1_get_invalidate_req()
205 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_1_init_system_aperture_regs()
217 tmp = REG_SET_FIELD(tm in mmhub_v3_0_1_init_tlb_regs()
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H A Dmmhub_v3_0_2.c81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v3_0_2_get_invalidate_req()
83 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v3_0_2_get_invalidate_req()
84 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v3_0_2_get_invalidate_req()
85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v3_0_2_get_invalidate_req()
86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v3_0_2_get_invalidate_req()
87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v3_0_2_get_invalidate_req()
88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v3_0_2_get_invalidate_req()
89 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v3_0_2_get_invalidate_req()
198 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_2_init_system_aperture_regs()
210 tmp = REG_SET_FIELD(tm in mmhub_v3_0_2_init_tlb_regs()
[all...]
H A Dgfxhub_v3_0.c60 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v3_0_get_invalidate_req()
62 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v3_0_get_invalidate_req()
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v3_0_get_invalidate_req()
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v3_0_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v3_0_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v3_0_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v3_0_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v3_0_get_invalidate_req()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_init_tlb_regs()
193 tmp = REG_SET_FIELD(tm in gfxhub_v3_0_init_tlb_regs()
[all...]
H A Dgfxhub_v3_0_3.c63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v3_0_3_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v3_0_3_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v3_0_3_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v3_0_3_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v3_0_3_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v3_0_3_get_invalidate_req()
70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v3_0_3_get_invalidate_req()
71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v3_0_3_get_invalidate_req()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_3_init_tlb_regs()
198 tmp = REG_SET_FIELD(tm in gfxhub_v3_0_3_init_tlb_regs()
[all...]
H A Dgfxhub_v2_0.c61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_0_get_invalidate_req()
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_0_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_0_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_0_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tm in gfxhub_v2_0_init_tlb_regs()
[all...]
H A Dgfxhub_v1_0.c161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
163 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
165 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
167 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
169 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
180 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
181 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_0_init_cache_regs()
185 tmp = REG_SET_FIELD(tm in gfxhub_v1_0_init_cache_regs()
[all...]
H A Dmmhub_v3_0.c81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v3_0_get_invalidate_req()
83 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v3_0_get_invalidate_req()
84 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v3_0_get_invalidate_req()
85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v3_0_get_invalidate_req()
86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v3_0_get_invalidate_req()
87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v3_0_get_invalidate_req()
88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v3_0_get_invalidate_req()
89 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v3_0_get_invalidate_req()
206 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_init_system_aperture_regs()
218 tmp = REG_SET_FIELD(tm in mmhub_v3_0_init_tlb_regs()
[all...]
H A Dmmhub_v2_3.c64 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_3_get_invalidate_req()
66 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v2_3_get_invalidate_req()
67 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v2_3_get_invalidate_req()
68 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v2_3_get_invalidate_req()
69 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v2_3_get_invalidate_req()
70 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v2_3_get_invalidate_req()
71 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v2_3_get_invalidate_req()
72 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_3_get_invalidate_req()
180 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_3_init_system_aperture_regs()
192 tmp = REG_SET_FIELD(tm in mmhub_v2_3_init_tlb_regs()
[all...]
H A Dmmhub_v2_0.c125 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
127 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v2_0_get_invalidate_req()
128 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v2_0_get_invalidate_req()
129 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v2_0_get_invalidate_req()
130 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v2_0_get_invalidate_req()
131 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v2_0_get_invalidate_req()
132 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v2_0_get_invalidate_req()
133 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
250 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
262 tmp = REG_SET_FIELD(tm in mmhub_v2_0_init_tlb_regs()
[all...]
H A Dhdp_v5_0.c67 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
69 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
87 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cnt in hdp_v5_0_update_mem_power_gating()
[all...]
H A Dhdp_v6_0.c56 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v6_0_update_clock_gating()
61 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
63 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
65 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
67 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
69 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
71 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cnt in hdp_v6_0_update_clock_gating()
[all...]
H A Dnbio_v7_9.c92 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, in nbio_v7_9_sdma_doorbell_range()
95 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, in nbio_v7_9_sdma_doorbell_range()
98 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, in nbio_v7_9_sdma_doorbell_range()
101 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, in nbio_v7_9_sdma_doorbell_range()
109 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
112 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
115 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
126 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
129 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
132 doorbell_ctrl = REG_SET_FIELD(doorbell_ctr in nbio_v7_9_sdma_doorbell_range()
[all...]
H A Dhdp_v5_2.c58 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
60 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
65 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
67 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
69 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
71 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cnt in hdp_v5_2_update_mem_power_gating()
[all...]
H A Dlsdma_v6_0.c56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v6_0_copy_mem()
57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_copy_mem()
58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v6_0_copy_mem()
59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
61 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0); in lsdma_v6_0_copy_mem()
62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v6_0_copy_mem()
88 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v6_0_fill_mem()
89 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_fill_mem()
90 tmp = REG_SET_FIELD(tm in lsdma_v6_0_fill_mem()
[all...]
H A Dmmhub_v1_8.c184 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_8_init_system_aperture_regs()
200 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, in mmhub_v1_8_init_tlb_regs()
202 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
204 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
208 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_8_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in mmhub_v1_8_init_tlb_regs()
228 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_8_init_cache_regs()
229 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, in mmhub_v1_8_init_cache_regs()
232 tmp = REG_SET_FIELD(tm in mmhub_v1_8_init_cache_regs()
[all...]
H A Dih_v6_0.c101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in force_update_wptr_for_self_int()
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in ih_v6_0_toggle_ring_interrupts()
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in ih_v6_0_toggle_ring_interrupts()
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_0_rb_cntl()
193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_0_rb_cntl()
195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_0_rb_cntl()
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in ih_v6_0_rb_cntl()
201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cnt in ih_v6_0_rb_cntl()
[all...]
H A Dih_v6_1.c101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in force_update_wptr_for_self_int()
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in ih_v6_1_toggle_ring_interrupts()
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in ih_v6_1_toggle_ring_interrupts()
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_1_rb_cntl()
193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_1_rb_cntl()
195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_1_rb_cntl()
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in ih_v6_1_rb_cntl()
201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cnt in ih_v6_1_rb_cntl()
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H A Dgfxhub_v2_1.c64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_1_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_1_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_1_get_invalidate_req()
70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_1_get_invalidate_req()
71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
72 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
195 tmp = REG_SET_FIELD(tm in gfxhub_v2_1_init_tlb_regs()
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H A Dgfxhub_v1_2.c175 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_2_xcc_init_system_aperture_regs()
204 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
208 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
212 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
214 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_2_xcc_init_tlb_regs()
229 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
230 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_2_xcc_init_cache_regs()
232 tmp = REG_SET_FIELD(tm in gfxhub_v1_2_xcc_init_cache_regs()
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H A Dmmhub_v1_0.c132 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
152 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in mmhub_v1_0_init_tlb_regs()
166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs()
169 tmp = REG_SET_FIELD(tm in mmhub_v1_0_init_cache_regs()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v2_1.c61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_1_get_invalidate_req()
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_1_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_1_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_1_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
193 tmp = REG_SET_FIELD(tm in gfxhub_v2_1_init_tlb_regs()
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H A Dgfxhub_v2_0.c61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_0_get_invalidate_req()
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_0_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_0_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_0_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tm in gfxhub_v2_0_init_tlb_regs()
[all...]
H A Dgfxhub_v1_0.c126 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
128 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v1_0_init_tlb_regs()
133 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
135 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
149 tmp = REG_SET_FIELD(tm in gfxhub_v1_0_init_cache_regs()
[all...]
H A Dmmhub_v2_0.c102 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
104 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v2_0_get_invalidate_req()
105 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v2_0_get_invalidate_req()
106 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v2_0_get_invalidate_req()
107 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v2_0_get_invalidate_req()
108 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v2_0_get_invalidate_req()
109 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v2_0_get_invalidate_req()
110 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
226 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
238 tmp = REG_SET_FIELD(tm in mmhub_v2_0_init_tlb_regs()
[all...]
H A Dmmhub_v1_0.c131 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
143 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
147 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
149 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in mmhub_v1_0_init_tlb_regs()
150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
152 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in mmhub_v1_0_init_tlb_regs()
166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
167 tmp = REG_SET_FIELD(tm in mmhub_v1_0_init_cache_regs()
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