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Searched refs:REG_SET (Results 1 - 25 of 155) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c61 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
64 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
120 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
124 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
133 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
149 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp3_program_surface_flip_and_addr()
153 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
157 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
161 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRES in hubp3_program_surface_flip_and_addr()
[all...]
H A Ddcn30_dpp_cm.c100 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
102 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
108 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
110 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
112 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
117 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg); in dpp3_program_gammcor_lut()
119 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green); in dpp3_program_gammcor_lut()
121 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
126 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg); in dpp3_program_gammcor_lut()
128 REG_SET(CM_GAMCOR_LUT_DAT in dpp3_program_gammcor_lut()
[all...]
H A Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_configure_ogam_lut()
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
200 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
210 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg); in dwb3_program_ogam_pwl()
220 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green); in dwb3_program_ogam_pwl()
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
228 REG_SET(DWB_OGAM_LUT_DAT in dwb3_program_ogam_pwl()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c57 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
60 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
116 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
120 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
125 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
145 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp3_program_surface_flip_and_addr()
149 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
153 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
157 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRES in hubp3_program_surface_flip_and_addr()
[all...]
H A Ddcn30_dpp_cm.c97 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
99 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
105 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
107 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
109 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
114 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg); in dpp3_program_gammcor_lut()
116 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green); in dpp3_program_gammcor_lut()
118 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
123 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg); in dpp3_program_gammcor_lut()
125 REG_SET(CM_GAMCOR_LUT_DAT in dpp3_program_gammcor_lut()
[all...]
H A Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_configure_ogam_lut()
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
200 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
210 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg); in dwb3_program_ogam_pwl()
220 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green); in dwb3_program_ogam_pwl()
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
228 REG_SET(DWB_OGAM_LUT_DAT in dwb3_program_ogam_pwl()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c61 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
63 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
65 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
223 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
227 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
230 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
231 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
234 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); in mpc1_insert_plane()
248 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); in mpc1_insert_plane()
314 REG_SET(MPCC_BOT_SE in mpc1_remove_mpcc()
[all...]
H A Ddcn10_hubp.c396 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
400 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
405 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
409 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
425 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
429 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
433 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
437 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
442 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
446 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_ in hubp1_program_surface_flip_and_addr()
[all...]
H A Ddcn10_dpp_cm.c100 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
154 REG_SET( in program_gamut_remap()
201 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
235 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
323 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
338 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); in dpp1_cm_program_regamma_lut()
339 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); in dpp1_cm_program_regamma_lut()
340 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); in dpp1_cm_program_regamma_lut()
342 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); in dpp1_cm_program_regamma_lut()
343 REG_SET(CM_RGAM_LUT_DAT in dpp1_cm_program_regamma_lut()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
229 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
233 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
236 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
240 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); in mpc1_insert_plane()
254 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); in mpc1_insert_plane()
320 REG_SET(MPCC_BOT_SE in mpc1_remove_mpcc()
[all...]
H A Ddcn10_hubp.c396 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
400 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
405 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
409 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
425 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
429 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
433 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
437 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
442 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
446 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_ in hubp1_program_surface_flip_and_addr()
[all...]
H A Ddcn10_dpp_cm.c100 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
154 REG_SET( in program_gamut_remap()
201 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
235 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
323 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
338 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); in dpp1_cm_program_regamma_lut()
339 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); in dpp1_cm_program_regamma_lut()
340 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); in dpp1_cm_program_regamma_lut()
342 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); in dpp1_cm_program_regamma_lut()
343 REG_SET(CM_RGAM_LUT_DAT in dpp1_cm_program_regamma_lut()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c75 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
77 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
82 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
89 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
H A Ddcn20_mpc.c66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
143 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
183 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
199 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
242 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
279 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
294 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc20_configure_ogam_lut()
389 REG_SET(MPCC_OGAM_LUT_DAT in mpc20_program_ogam_pwl()
[all...]
H A Ddcn20_optc.c202 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
230 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
246 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); in optc2_set_odm_combine()
261 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
272 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); in optc2_set_odm_combine()
316 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_triplebuffer_lock()
319 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_lock()
322 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_lock()
335 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_unlock()
338 REG_SET(OTG_VUPDATE_KEEPOU in optc2_triplebuffer_unlock()
[all...]
H A Ddcn20_hubp.c65 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, in hubp2_set_vm_system_aperture_settings()
68 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
71 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
91 REG_SET(BLANK_OFFSET_1, 0, in hubp2_program_deadline()
94 REG_SET(DST_DIMENSIONS, 0, in hubp2_program_deadline()
101 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, in hubp2_program_deadline()
105 REG_SET(VBLANK_PARAMETERS_1, 0, in hubp2_program_deadline()
109 REG_SET(NOM_PARAMETERS_0, 0, in hubp2_program_deadline()
113 REG_SET(NOM_PARAMETERS_1, 0, in hubp2_program_deadline()
116 REG_SET(NOM_PARAMETERS_ in hubp2_program_deadline()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c75 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
77 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
82 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
89 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
H A Ddcn20_mpc.c66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
182 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
198 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
241 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
293 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc20_configure_ogam_lut()
388 REG_SET(MPCC_OGAM_LUT_DAT in mpc20_program_ogam_pwl()
[all...]
H A Ddcn20_optc.c142 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
183 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
199 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); in optc2_set_odm_combine()
214 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
225 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); in optc2_set_odm_combine()
293 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_align_vblanks()
303 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
331 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
353 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
377 REG_SET(OTG_MASTER_UPDATE_LOC in optc2_align_vblanks()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hubbub.c167 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub31_program_urgent_watermarks()
181 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub31_program_urgent_watermarks()
191 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub31_program_urgent_watermarks()
201 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, in hubbub31_program_urgent_watermarks()
211 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub31_program_urgent_watermarks()
225 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, in hubbub31_program_urgent_watermarks()
235 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub31_program_urgent_watermarks()
245 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0, in hubbub31_program_urgent_watermarks()
255 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub31_program_urgent_watermarks()
269 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_ in hubbub31_program_urgent_watermarks()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hubbub.c184 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub32_program_urgent_watermarks()
198 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub32_program_urgent_watermarks()
208 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub32_program_urgent_watermarks()
218 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, in hubbub32_program_urgent_watermarks()
228 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub32_program_urgent_watermarks()
242 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, in hubbub32_program_urgent_watermarks()
252 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub32_program_urgent_watermarks()
262 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0, in hubbub32_program_urgent_watermarks()
272 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub32_program_urgent_watermarks()
286 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_ in hubbub32_program_urgent_watermarks()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c129 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
132 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
180 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
183 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
195 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
199 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
202 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
205 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
212 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
H A Ddce_transform.c120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in setup_scaling_configuration()
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); in setup_scaling_configuration()
154 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in dce60_setup_scaling_configuration()
226 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
344 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
347 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
367 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
370 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
445 REG_SET(SCL_VERT_FILTER_CONTROL, 0, in dce_transform_set_scaler()
460 REG_SET(SCL_HORZ_FILTER_CONTRO in dce_transform_set_scaler()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c127 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
130 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
178 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
181 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
193 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
197 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
200 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
203 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
210 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
H A Ddce_transform.c120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in setup_scaling_configuration()
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); in setup_scaling_configuration()
154 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in dce60_setup_scaling_configuration()
226 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
344 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
347 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
367 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
370 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
445 REG_SET(SCL_VERT_FILTER_CONTROL, 0, in dce_transform_set_scaler()
460 REG_SET(SCL_HORZ_FILTER_CONTRO in dce_transform_set_scaler()
[all...]

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