Searched refs:REG_OFFSET_MASK (Results 1 - 6 of 6) sorted by relevance
| /kernel/linux/linux-5.10/drivers/reset/ |
| H A D | reset-intel-gw.c | 18 #define REG_OFFSET_MASK GENMASK(31, 16) macro
54 *rst_req = FIELD_GET(REG_OFFSET_MASK, id); in id_to_reg_and_bit_offsets()
144 id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]); in intel_reset_xlate()
213 data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]); in intel_reset_probe()
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| /kernel/linux/linux-6.6/drivers/reset/ |
| H A D | reset-intel-gw.c | 18 #define REG_OFFSET_MASK GENMASK(31, 16) macro
54 *rst_req = FIELD_GET(REG_OFFSET_MASK, id); in id_to_reg_and_bit_offsets()
144 id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]); in intel_reset_xlate()
213 data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]); in intel_reset_probe()
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| /kernel/linux/linux-5.10/drivers/mfd/ |
| H A D | intel_soc_pmic_chtwc.c | 22 #define REG_OFFSET_MASK GENMASK(7, 0) macro
83 ret = i2c_smbus_read_byte_data(client, reg & REG_OFFSET_MASK); in cht_wc_byte_reg_read()
105 ret = i2c_smbus_write_byte_data(client, reg & REG_OFFSET_MASK, val); in cht_wc_byte_reg_write()
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| H A D | intel_soc_pmic_bxtwc.c | 23 #define REG_OFFSET_MASK 0xFF macro
291 reg &= REG_OFFSET_MASK; in regmap_ipc_byte_reg_read()
321 reg &= REG_OFFSET_MASK; in regmap_ipc_byte_reg_write()
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| /kernel/linux/linux-6.6/drivers/mfd/ |
| H A D | intel_soc_pmic_chtwc.c | 23 #define REG_OFFSET_MASK GENMASK(7, 0) macro
84 ret = i2c_smbus_read_byte_data(client, reg & REG_OFFSET_MASK); in cht_wc_byte_reg_read()
106 ret = i2c_smbus_write_byte_data(client, reg & REG_OFFSET_MASK, val); in cht_wc_byte_reg_write()
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| H A D | intel_soc_pmic_bxtwc.c | 24 #define REG_OFFSET_MASK GENMASK(7, 0) macro
292 reg &= REG_OFFSET_MASK; in regmap_ipc_byte_reg_read()
322 reg &= REG_OFFSET_MASK; in regmap_ipc_byte_reg_write()
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