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Searched refs:REG_OFFSET (Results 1 - 25 of 38) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dmdfld_dsi_output.h86 #define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400) macro
89 #define MIPI_DEVICE_READY_REG(pipe) (0xb000 + REG_OFFSET(pipe))
90 #define MIPI_INTR_STAT_REG(pipe) (0xb004 + REG_OFFSET(pipe))
91 #define MIPI_INTR_EN_REG(pipe) (0xb008 + REG_OFFSET(pipe))
92 #define MIPI_DSI_FUNC_PRG_REG(pipe) (0xb00c + REG_OFFSET(pipe))
93 #define MIPI_HS_TX_TIMEOUT_REG(pipe) (0xb010 + REG_OFFSET(pipe))
94 #define MIPI_LP_RX_TIMEOUT_REG(pipe) (0xb014 + REG_OFFSET(pipe))
95 #define MIPI_TURN_AROUND_TIMEOUT_REG(pipe) (0xb018 + REG_OFFSET(pipe))
96 #define MIPI_DEVICE_RESET_TIMER_REG(pipe) (0xb01c + REG_OFFSET(pipe))
97 #define MIPI_DPI_RESOLUTION_REG(pipe) (0xb020 + REG_OFFSET(pip
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/kernel/linux/linux-5.10/arch/arm64/kvm/
H A Dregmap.c17 #define REG_OFFSET(_reg) \ macro
20 #define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
30 REG_OFFSET(pc)
38 REG_OFFSET(compat_r8_fiq), /* r8 */
39 REG_OFFSET(compat_r9_fiq), /* r9 */
40 REG_OFFSET(compat_r10_fiq), /* r10 */
41 REG_OFFSET(compat_r11_fiq), /* r11 */
42 REG_OFFSET(compat_r12_fiq), /* r12 */
43 REG_OFFSET(compat_sp_fiq), /* r13 */
44 REG_OFFSET(compat_lr_fi
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/kernel/linux/linux-5.10/arch/mips/ar7/
H A Dirq.c19 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) macro
22 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
24 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
26 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
30 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
31 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
/kernel/linux/linux-6.6/arch/mips/ar7/
H A Dirq.c19 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) macro
22 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
24 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
26 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
30 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
31 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
/kernel/linux/linux-5.10/arch/arm/mach-ixp4xx/
H A Dgtwx5715-setup.c71 #define REG_OFFSET 3 macro
73 #define REG_OFFSET 0 macro
98 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Davila-setup.c89 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
98 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dcoyote-setup.c67 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
104 (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET); in coyote_init()
H A Ddsmg600-setup.c137 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
146 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dixdp425-setup.c162 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
171 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dnas100d-setup.c140 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
149 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dnslu2-setup.c160 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
169 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dvulcan-setup.c84 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
93 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Domixp-setup.c127 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
135 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
H A Dfsg-setup.c100 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
109 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dwg302v2-setup.c62 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dgateway7001-setup.c61 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
/kernel/linux/linux-5.10/arch/arm/mach-ixp4xx/include/mach/
H A Dplatform.h23 #define REG_OFFSET 0 macro
25 #define REG_OFFSET 3 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn21.c41 #define DMUB_SR(reg) REG_OFFSET(reg),
H A Ddmub_dcn302.c41 #define DMUB_SR(reg) REG_OFFSET(reg),
H A Ddmub_dcn301.c41 #define DMUB_SR(reg) REG_OFFSET(reg),
H A Ddmub_dcn303.c23 #define DMUB_SR(reg) REG_OFFSET(reg),
/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-pcf8523.c35 #define REG_OFFSET 0x0e macro
305 err = pcf8523_read(client, REG_OFFSET, &value); in pcf8523_rtc_read_offset()
330 return pcf8523_write(client, REG_OFFSET, value); in pcf8523_rtc_set_offset()
/kernel/linux/linux-5.10/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c26 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ macro
83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set()
101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_reset()
340 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); in plgpio_irq_set_type()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn21.c41 #define DMUB_SR(reg) REG_OFFSET(reg),
/kernel/linux/linux-6.6/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c28 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ macro
85 u32 reg_off = REG_OFFSET(0, reg, pin); in is_plgpio_set()
96 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_set()
106 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_reset()
349 reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); in plgpio_irq_set_type()

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