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Searched refs:REG_FPGA0_XB_RF_INT_OE (Results 1 - 11 of 11) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8192e.c1079 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING in rtl8192eu_phy_iqcalibrate()
1118 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1120 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
H A Drtl8xxxu_regs.h873 #define REG_FPGA0_XB_RF_INT_OE 0x0864 macro
H A Drtl8xxxu_core.c2400 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; in rtl8xxxu_init_phy_rf()
3135 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE in rtl8xxxu_phy_iqcalibrate()
3184 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8xxxu_phy_iqcalibrate()
3186 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8xxxu_phy_iqcalibrate()
H A Drtl8xxxu_8723b.c903 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE in rtl8723bu_phy_iqcalibrate()
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8188e.c791 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING in rtl8188eu_phy_iqcalibrate()
842 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8188eu_phy_iqcalibrate()
844 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8188eu_phy_iqcalibrate()
H A Drtl8xxxu_8710b.c774 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8710bu_config_channel()
777 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8710bu_config_channel()
1296 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING in rtl8710bu_phy_iqcalibrate()
H A Drtl8xxxu_8192e.c1091 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING in rtl8192eu_phy_iqcalibrate()
1130 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1132 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
H A Drtl8xxxu_8188f.c463 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8188f_spur_calibration()
1088 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE in rtl8188fu_phy_iqcalibrate()
H A Drtl8xxxu_regs.h916 #define REG_FPGA0_XB_RF_INT_OE 0x0864 macro
H A Drtl8xxxu_core.c2466 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; in rtl8xxxu_init_phy_rf()
3224 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE in rtl8xxxu_phy_iqcalibrate()
3273 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8xxxu_phy_iqcalibrate()
3275 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8xxxu_phy_iqcalibrate()
H A Drtl8xxxu_8723b.c935 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE in rtl8723bu_phy_iqcalibrate()

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