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Searched refs:REG_FIELD_MASK (Results 1 - 9 of 9) sorted by relevance

/kernel/linux/linux-6.6/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_masks.h129 REG_FIELD_MASK(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE, HOP4_PAGE_SIZE)
131 REG_FIELD_MASK(DCORE0_HMMU0_STLB_HOP_CONFIGURATION, ONLY_LARGE_PAGE)
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h33 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
130 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
H A Damdgpu.h1122 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK macro
1125 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1126 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1129 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1132 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1135 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
H A Dmxgpu_vi.c321 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_send_ack()
368 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_rcv_msg()
390 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); in xgpu_vi_poll_ack()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h55 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
63 ~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \
188 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
H A Damdgpu.h1225 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK macro
1228 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1229 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1232 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1235 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1238 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
H A Dmxgpu_vi.c323 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_send_ack()
370 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_rcv_msg()
392 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); in xgpu_vi_poll_ack()
/kernel/linux/linux-5.10/drivers/misc/habanalabs/common/
H A Dhabanalabs.h1326 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK macro
1329 ~REG_FIELD_MASK(reg, field)) | \
/kernel/linux/linux-6.6/drivers/accel/habanalabs/common/
H A Dhabanalabs.h2549 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK macro
2552 ~REG_FIELD_MASK(reg, field)) | \

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