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Searched refs:REG_CLR (Results 1 - 13 of 13) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/mach-imx/
H A Danatop.c17 #define REG_CLR 0x8 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/kernel/linux/linux-6.6/arch/arm/mach-imx/
H A Danatop.c17 #define REG_CLR 0x8 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/kernel/linux/linux-5.10/drivers/gpu/drm/mxsfb/
H A Dmxsfb_kms.c166 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_disable_controller()
189 writel(mask, addr + REG_CLR); in clear_poll_bit()
201 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_reset_block()
247 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_mode_set_nofb()
397 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_enable_vblank()
408 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
409 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
H A Dmxsfb_drv.c273 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
274 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
290 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_handler()
H A Dmxsfb_regs.h13 #define REG_CLR 8 macro
/kernel/linux/linux-5.10/drivers/thermal/
H A Dimx_thermal.c21 #define REG_CLR 0x8 macro
225 regmap_write(map, soc_data->panic_alarm_ctrl + REG_CLR, in imx_set_panic_temp()
245 regmap_write(map, soc_data->high_alarm_ctrl + REG_CLR, in imx_set_alarm_temp()
676 regmap_write(map, IMX6_MISC1 + REG_CLR, in imx_thermal_probe()
707 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
709 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
711 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
765 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
775 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
871 ret = regmap_write(map, socdata->sensor_ctrl + REG_CLR, in imx_thermal_runtime_suspend()
[all...]
/kernel/linux/linux-6.6/drivers/thermal/
H A Dimx_thermal.c21 #define REG_CLR 0x8 macro
227 regmap_write(map, soc_data->panic_alarm_ctrl + REG_CLR, in imx_set_panic_temp()
247 regmap_write(map, soc_data->high_alarm_ctrl + REG_CLR, in imx_set_alarm_temp()
629 regmap_write(map, IMX6_MISC1 + REG_CLR, in imx_thermal_probe()
660 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
662 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
664 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
719 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
729 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
825 ret = regmap_write(map, socdata->sensor_ctrl + REG_CLR, in imx_thermal_runtime_suspend()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/mxsfb/
H A Dmxsfb_kms.c215 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_disable_controller()
238 writel(mask, addr + REG_CLR); in clear_poll_bit()
256 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_reset_block()
269 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_reset_block()
428 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_enable_vblank()
439 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
440 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
H A Dmxsfb_drv.c175 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_handler()
187 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
188 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
H A Dmxsfb_regs.h13 #define REG_CLR 8 macro
H A Dlcdif_regs.h12 #define REG_CLR 8 macro
H A Dlcdif_kms.c397 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR); in lcdif_reset_block()
/kernel/linux/linux-6.6/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-lvds-phy.c19 #define REG_CLR 0x8 macro
154 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
157 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()

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