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Help
Searched
refs:REG_BIT
(Results
1 - 25
of
30
) sorted by relevance
1
2
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H
A
D
intel_psr_regs.h
13
#define EXITLINE_ENABLE
REG_BIT
(31)
27
#define EDP_PSR_ENABLE
REG_BIT
(31)
28
#define BDW_PSR_SINGLE_FRAME
REG_BIT
(30)
29
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK
REG_BIT
(29) /* SW can't modify */
30
#define EDP_PSR_LINK_STANDBY
REG_BIT
(27)
38
#define EDP_PSR_SKIP_AUX_EXIT
REG_BIT
(12)
39
#define EDP_PSR_TP_MASK
REG_BIT
(11)
42
#define EDP_PSR_CRC_ENABLE
REG_BIT
(10) /* BDW+ */
72
#define TGL_PSR_ERROR
REG_BIT
(2)
73
#define TGL_PSR_POST_EXIT
REG_BIT
(
[all...]
H
A
D
intel_hdcp_regs.h
13
#define HDCP_AKSV_SEND_TRIGGER
REG_BIT
(31)
14
#define HDCP_CLEAR_KEYS_TRIGGER
REG_BIT
(30)
15
#define HDCP_KEY_LOAD_TRIGGER
REG_BIT
(8)
17
#define HDCP_FUSE_IN_PROGRESS
REG_BIT
(7)
18
#define HDCP_FUSE_ERROR
REG_BIT
(6)
19
#define HDCP_FUSE_DONE
REG_BIT
(5)
20
#define HDCP_KEY_LOAD_STATUS
REG_BIT
(1)
21
#define HDCP_KEY_LOAD_DONE
REG_BIT
(0)
27
#define HDCP_TRANSA_REP_PRESENT
REG_BIT
(31)
28
#define HDCP_TRANSB_REP_PRESENT
REG_BIT
(3
[all...]
H
A
D
intel_dvo_regs.h
15
#define DVO_ENABLE
REG_BIT
(31)
16
#define DVO_PIPE_SEL_MASK
REG_BIT
(30)
22
#define DVO_INTERRUPT_SELECT
REG_BIT
(27)
23
#define DVO_DEDICATED_INT_ENABLE
REG_BIT
(26)
25
#define DVO_USE_VGA_SYNC
REG_BIT
(15)
26
#define DVO_DATA_ORDER_MASK
REG_BIT
(14)
29
#define DVO_VSYNC_DISABLE
REG_BIT
(11)
30
#define DVO_HSYNC_DISABLE
REG_BIT
(10)
31
#define DVO_VSYNC_TRISTATE
REG_BIT
(9)
32
#define DVO_HSYNC_TRISTATE
REG_BIT
(
[all...]
H
A
D
intel_dsb_regs.h
18
#define DSB_ENABLE
REG_BIT
(31)
19
#define DSB_BUF_REITERATE
REG_BIT
(29)
20
#define DSB_WAIT_FOR_VBLANK
REG_BIT
(28)
21
#define DSB_WAIT_FOR_LINE_IN
REG_BIT
(27)
22
#define DSB_HALT
REG_BIT
(16)
23
#define DSB_NON_POSTED
REG_BIT
(8)
24
#define DSB_STATUS_BUSY
REG_BIT
(0)
26
#define DSB_MMIO_DEAD_CLOCKS_ENABLE
REG_BIT
(31)
32
#define DSB_POLL_ENABLE
REG_BIT
(31)
41
#define DSB_ATS_FAULT_INT_EN
REG_BIT
(2
[all...]
H
A
D
intel_cx0_phy_regs.h
20
#define XELPDP_PORT_M2P_TRANSACTION_PENDING
REG_BIT
(31)
27
#define XELPDP_PORT_M2P_TRANSACTION_RESET
REG_BIT
(15)
35
#define XELPDP_PORT_P2M_RESPONSE_READY
REG_BIT
(31)
41
#define XELPDP_PORT_P2M_ERROR_SET
REG_BIT
(15)
62
#define XELPDP_PORT_BUF_D2D_LINK_ENABLE
REG_BIT
(29)
63
#define XELPDP_PORT_BUF_D2D_LINK_STATE
REG_BIT
(28)
64
#define XELPDP_PORT_BUF_SOC_PHY_READY
REG_BIT
(24)
69
#define XELPDP_PORT_REVERSAL
REG_BIT
(16)
70
#define XELPDP_PORT_BUF_IO_SELECT_TBT
REG_BIT
(11)
71
#define XELPDP_PORT_BUF_PHY_IDLE
REG_BIT
(
[all...]
H
A
D
intel_dp_aux_regs.h
53
#define DP_AUX_CH_CTL_SEND_BUSY
REG_BIT
(31)
54
#define DP_AUX_CH_CTL_DONE
REG_BIT
(30)
55
#define DP_AUX_CH_CTL_INTERRUPT
REG_BIT
(29)
56
#define DP_AUX_CH_CTL_TIME_OUT_ERROR
REG_BIT
(28)
63
#define DP_AUX_CH_CTL_RECEIVE_ERROR
REG_BIT
(25)
68
#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST
REG_BIT
(19) /* mtl+ */
69
#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS
REG_BIT
(18) /* mtl+ */
70
#define DP_AUX_CH_CTL_AUX_AKSV_SELECT
REG_BIT
(15)
71
#define DP_AUX_CH_CTL_MANCHESTER_TEST
REG_BIT
(14) /* pre-hsw */
72
#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL
REG_BIT
(1
[all...]
H
A
D
intel_snps_phy_regs.h
29
#define SNPS_PHY_MPLLB_FORCE_EN
REG_BIT
(31)
30
#define SNPS_PHY_MPLLB_DIV_CLK_EN
REG_BIT
(30)
31
#define SNPS_PHY_MPLLB_DIV5_CLK_EN
REG_BIT
(29)
35
#define SNPS_PHY_MPLLB_PMIX_EN
REG_BIT
(10)
36
#define SNPS_PHY_MPLLB_DP2_MODE
REG_BIT
(9)
37
#define SNPS_PHY_MPLLB_WORD_DIV2_EN
REG_BIT
(8)
39
#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL
REG_BIT
(0)
42
#define SNPS_PHY_MPLLB_FRACN_EN
REG_BIT
(31)
43
#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN
REG_BIT
(30)
51
#define SNPS_PHY_MPLLB_SSC_EN
REG_BIT
(3
[all...]
H
A
D
intel_lvds_regs.h
17
#define LVDS_PORT_EN
REG_BIT
(31)
19
#define LVDS_PIPE_SEL_MASK
REG_BIT
(30)
24
#define LVDS_ENABLE_DITHER
REG_BIT
(25)
26
#define LVDS_VSYNC_POLARITY
REG_BIT
(21)
27
#define LVDS_HSYNC_POLARITY
REG_BIT
(20)
30
#define LVDS_BORDER_ENABLE
REG_BIT
(15)
63
#define LVDS_DETECTED
REG_BIT
(1)
H
A
D
intel_audio_regs.h
12
#define G4X_ELD_VALID
REG_BIT
(14)
15
#define G4X_ELD_ACK
REG_BIT
(4)
28
#define IBX_ELD_ACK
REG_BIT
(4)
30
#define IBX_CP_READY(port)
REG_BIT
(((port) - 1) * 4 + 1)
31
#define IBX_ELD_VALID(port)
REG_BIT
(((port) - 1) * 4 + 0)
58
#define AUD_CONFIG_N_VALUE_INDEX
REG_BIT
(29)
59
#define AUD_CONFIG_N_PROG_ENABLE
REG_BIT
(28)
81
#define AUD_CONFIG_DISABLE_NCTS
REG_BIT
(3)
94
#define AUD_M_CTS_M_VALUE_INDEX
REG_BIT
(21)
95
#define AUD_M_CTS_M_PROG_ENABLE
REG_BIT
(2
[all...]
H
A
D
intel_pps_regs.h
22
#define PP_ON
REG_BIT
(31)
30
#define PP_READY
REG_BIT
(30)
35
#define PP_CYCLE_DELAY_ACTIVE
REG_BIT
(27)
52
#define EDP_FORCE_VDD
REG_BIT
(3)
53
#define EDP_BLC_ENABLE
REG_BIT
(2)
54
#define PANEL_POWER_RESET
REG_BIT
(1)
55
#define PANEL_POWER_ON
REG_BIT
(0)
H
A
D
intel_dmc_regs.h
19
#define PIPEDMC_ENABLE
REG_BIT
(0)
22
#define PIPEDMC_ENABLE_MTL(pipe)
REG_BIT
(((pipe) - PIPE_A) * 4)
53
#define DMC_EVT_CTL_ENABLE
REG_BIT
(31)
54
#define DMC_EVT_CTL_RECURRING
REG_BIT
(30)
H
A
D
intel_hti_regs.h
13
#define HDPORT_DDI_USED(phy)
REG_BIT
(2 * (phy) + 1)
14
#define HDPORT_ENABLED
REG_BIT
(0)
H
A
D
skl_watermark_regs.h
19
#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN
REG_BIT
(16) /* tgl+ */
36
#define MBUS_JOIN
REG_BIT
(31)
37
#define MBUS_HASHING_MODE_MASK
REG_BIT
(30)
144
#define DBUF_POWER_REQUEST
REG_BIT
(31)
145
#define DBUF_POWER_STATE
REG_BIT
(30)
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H
A
D
intel_gt_regs.h
78
#define GEN11_MCR_MULTICAST
REG_BIT
(31)
174
#define GEN12_PERF_FIX_BALANCING_CFE_DISABLE
REG_BIT
(15)
177
#define FF_DOP_CLOCK_GATE_DISABLE
REG_BIT
(1)
179
#define GEN12_REPLAY_MODE_GRANULARITY
REG_BIT
(0)
243
#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG
REG_BIT
(11)
351
#define AUX_INV
REG_BIT
(0)
416
#define DIS_SF_ROUND_NEAREST_EVEN
REG_BIT
(8)
419
#define TBIMR_FAST_CLIP
REG_BIT
(5)
422
#define VF_PREFETCH_TLB_DIS
REG_BIT
(5)
423
#define DIS_OVER_FETCH_CACHE
REG_BIT
(
[all...]
H
A
D
intel_engine_regs.h
48
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE
REG_BIT
(12)
49
#define GEN8_FF_DOP_CLOCK_GATE_DISABLE
REG_BIT
(10)
50
#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE
REG_BIT
(7)
51
#define GEN6_BSD_GO_INDICATOR
REG_BIT
(4)
52
#define GEN6_BSD_SLEEP_INDICATOR
REG_BIT
(3)
53
#define GEN6_BSD_SLEEP_FLUSH_DISABLE
REG_BIT
(2)
54
#define GEN6_PSMI_SLEEP_MSG_DISABLE
REG_BIT
(0)
74
#define ASYNC_FLIP_PERF_DISABLE
REG_BIT
(14)
75
#define MI_FLUSH_ENABLE
REG_BIT
(12)
76
#define TGL_NESTED_BB_EN
REG_BIT
(1
[all...]
H
A
D
intel_gpu_commands.h
137
#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) |
REG_BIT
(21))
157
#define MI_LRI_LRM_CS_MMIO
REG_BIT
(19)
158
#define MI_LRI_MMIO_REMAP_EN
REG_BIT
(17)
179
#define MI_LRR_SOURCE_CS_MMIO
REG_BIT
(18)
189
#define MI_BATCH_RESOURCE_STREAMER
REG_BIT
(10)
190
#define MI_BATCH_PREDICATE
REG_BIT
(15) /* HSW+ on RCS only*/
257
#define XY_FAST_COPY_BLT_D1_SRC_TILE4
REG_BIT
(31)
258
#define XY_FAST_COPY_BLT_D1_DST_TILE4
REG_BIT
(30)
309
#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH
REG_BIT
(9) /* gen12 */
374
#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG
REG_BIT
(
[all...]
H
A
D
intel_gtt.h
77
#define GEN6_PTE_VALID
REG_BIT
(0)
83
#define GEN6_PDE_VALID
REG_BIT
(0)
88
#define BYT_PTE_SNOOPED_BY_CPU_CACHES
REG_BIT
(2)
89
#define BYT_PTE_WRITEABLE
REG_BIT
(1)
140
#define CHV_PPAT_SNOOP
REG_BIT
(6)
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H
A
D
i915_reg.h
71
* Define bits using ``
REG_BIT
(N)``. Do **not** add ``_BIT`` suffix to the name.
109
* #define FOO_ENABLE
REG_BIT
(31)
120
#define DEPRESENT
REG_BIT
(9)
123
#define LMEM_INIT
REG_BIT
(7)
124
#define DRIVERFLR
REG_BIT
(31)
126
#define DRIVERFLR_STATUS
REG_BIT
(31)
586
#define PORT_PLL_ENABLE
REG_BIT
(31)
587
#define PORT_PLL_LOCK
REG_BIT
(30)
588
#define PORT_PLL_REF_SEL
REG_BIT
(27)
589
#define PORT_PLL_POWER_ENABLE
REG_BIT
(2
[all...]
H
A
D
i915_perf_oa_regs.h
147
#define GEN12_OAM_BUFFER_MEMORY_SELECT
REG_BIT
(0) /* 0: PPGTT, 1: GGTT */
151
#define GEN12_OAM_CONTEXT_CONTROL_TIMER_ENABLE
REG_BIT
(1)
152
#define GEN12_OAM_CONTEXT_CONTROL_COUNTER_RESUME
REG_BIT
(0)
156
#define GEN12_OAM_CONTROL_COUNTER_ENABLE
REG_BIT
(0)
159
#define GEN12_OAM_DEBUG_BUFFER_SIZE_SELECT
REG_BIT
(12)
160
#define GEN12_OAM_DEBUG_INCLUDE_CLK_RATIO
REG_BIT
(6)
161
#define GEN12_OAM_DEBUG_DISABLE_CLK_RATIO_REPORTS
REG_BIT
(5)
162
#define GEN12_OAM_DEBUG_DISABLE_GO_1_0_REPORTS
REG_BIT
(2)
163
#define GEN12_OAM_DEBUG_DISABLE_CTX_SWITCH_REPORTS
REG_BIT
(1)
166
#define GEN12_OAM_STATUS_COUNTER_OVERFLOW
REG_BIT
(
[all...]
H
A
D
intel_mchbar_regs.h
190
#define DG1_QCLK_REFERENCE
REG_BIT
(10)
220
#define PKG_PWR_LIM_1_EN
REG_BIT
(15)
241
#define DG1_GEAR_TYPE
REG_BIT
(16)
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/uc/abi/
H
A
D
guc_actions_slpc_abi.h
156
#define SLPC_GTPERF_TASK_ENABLED
REG_BIT
(0)
157
#define SLPC_DCC_TASK_ENABLED
REG_BIT
(11)
158
#define SLPC_IN_DCC
REG_BIT
(12)
159
#define SLPC_BALANCER_ENABLED
REG_BIT
(15)
160
#define SLPC_IBC_TASK_ENABLED
REG_BIT
(16)
161
#define SLPC_BALANCER_IA_LMT_ENABLED
REG_BIT
(17)
162
#define SLPC_BALANCER_IA_LMT_ACTIVE
REG_BIT
(18)
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H
A
D
intel_gpu_commands.h
141
#define MI_LRI_LRM_CS_MMIO
REG_BIT
(19)
159
#define MI_LRR_SOURCE_CS_MMIO
REG_BIT
(18)
169
#define MI_BATCH_RESOURCE_STREAMER
REG_BIT
(10)
170
#define MI_BATCH_PREDICATE
REG_BIT
(15) /* HSW+ on RCS only*/
240
#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH
REG_BIT
(9) /* gen12 */
297
#define BASE_ADDRESS_MODIFY
REG_BIT
(0)
300
#define PIPELINE_SELECT_MEDIA
REG_BIT
(0)
H
A
D
intel_gtt.h
74
#define GEN6_PTE_VALID
REG_BIT
(0)
80
#define GEN6_PDE_VALID
REG_BIT
(0)
85
#define BYT_PTE_SNOOPED_BY_CPU_CACHES
REG_BIT
(2)
86
#define BYT_PTE_WRITEABLE
REG_BIT
(1)
122
#define CHV_PPAT_SNOOP
REG_BIT
(6)
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/pxp/
H
A
D
intel_pxp_regs.h
19
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES
REG_BIT
(14)
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H
A
D
i915_reg.h
71
* Define bits using ``
REG_BIT
(N)``. Do **not** add ``_BIT`` suffix to the name.
109
* #define FOO_ENABLE
REG_BIT
(31)
120
*
REG_BIT
() - Prepare a u32 bit value
127
#define
REG_BIT
(__n) \
macro
158
* u32 and for consistency with REG_FIELD_GET(),
REG_BIT
() and REG_GENMASK().
175
* REG_FIELD_PREP(),
REG_BIT
() and REG_GENMASK().
564
#define BCS_SRC_Y
REG_BIT
(0)
565
#define BCS_DST_Y
REG_BIT
(1)
2083
#define ICL_PORT_TX_DW8_ODCC_CLK_SEL
REG_BIT
(31)
2089
#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP
REG_BIT
(
[all...]
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