| /kernel/linux/linux-5.10/drivers/net/ethernet/marvell/ |
| H A D | sky2.c | 1045 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in sky2_ramset()
1068 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in sky2_ramset()
1071 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in sky2_ramset()
1072 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); in sky2_ramset()
1330 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); in sky2_rx_stop()
1686 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), in sky2_hw_up()
2057 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in sky2_tx_reset()
2076 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in sky2_hw_down()
2423 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); in sky2_change_mtu()
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| H A D | skge.c | 2487 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in skge_ramset()
2503 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in skge_ramset()
2506 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in skge_ramset()
2640 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), in skge_rx_stop()
2681 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in skge_down()
2695 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in skge_down()
2698 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
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| H A D | skge.h | 492 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ enumerator
766 /* RB_CTRL 8 bit RAM Buffer Control Register */
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| H A D | sky2.h | 798 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ enumerator
963 /* RB_CTRL 8 bit RAM Buffer Control Register */
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| /kernel/linux/linux-6.6/drivers/net/ethernet/marvell/ |
| H A D | sky2.c | 1044 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in sky2_ramset()
1067 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in sky2_ramset()
1070 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in sky2_ramset()
1071 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); in sky2_ramset()
1329 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); in sky2_rx_stop()
1686 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), in sky2_hw_up()
2057 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in sky2_tx_reset()
2076 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in sky2_hw_down()
2423 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); in sky2_change_mtu()
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| H A D | skge.c | 2494 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in skge_ramset()
2510 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in skge_ramset()
2513 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in skge_ramset()
2647 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), in skge_rx_stop()
2688 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in skge_down()
2702 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in skge_down()
2705 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
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| H A D | skge.h | 492 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ enumerator
766 /* RB_CTRL 8 bit RAM Buffer Control Register */
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| H A D | sky2.h | 798 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ enumerator
963 /* RB_CTRL 8 bit RAM Buffer Control Register */
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