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Searched refs:R9A06G032_DIV_UART (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/renesas/
H A Dr9a06g032-clocks.c117 #define R9A06G032_DIV_UART 25 macro
288 .source = 1 + R9A06G032_DIV_UART,
629 if (clk->index == R9A06G032_DIV_UART || in r9a06g032_div_round_rate()
/kernel/linux/linux-6.6/drivers/clk/renesas/
H A Dr9a06g032-clocks.c241 #define R9A06G032_DIV_UART 25 macro
634 .source = 1 + R9A06G032_DIV_UART,
1002 if (clk->index == R9A06G032_DIV_UART || in r9a06g032_div_determine_rate()

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