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Searched refs:PP_ON (Results 1 - 22 of 22) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dpsb_lid.c31 } while ((pp_status & PP_ON) == 0 && in psb_lid_timer_func()
34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
47 } while ((pp_status & PP_ON) == 0); in psb_lid_timer_func()
H A Dpsb_intel_lvds.c225 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_set_power()
236 } while (pp_status & PP_ON); in psb_intel_lvds_set_power()
325 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_restore()
331 } while (pp_status & PP_ON); in psb_intel_lvds_restore()
H A Dcdv_intel_lvds.c119 } while ((pp_status & PP_ON) == 0); in cdv_intel_lvds_set_power()
130 } while (pp_status & PP_ON); in cdv_intel_lvds_set_power()
H A Doaktrail_lvds.c50 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); in oaktrail_lvds_set_power()
61 } while (pp_status & PP_ON); in oaktrail_lvds_set_power()
H A Dpsb_intel_reg.h151 # define PP_ON (1 << 31) macro
H A Dcdv_intel_dp.c419 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE; in cdv_intel_edp_panel_on()
445 u32 pp, idle_off_mask = PP_ON ; in cdv_intel_edp_panel_off()
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Dpsb_lid.c31 } while ((pp_status & PP_ON) == 0 && in psb_lid_timer_func()
34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
47 } while ((pp_status & PP_ON) == 0); in psb_lid_timer_func()
H A Dpsb_intel_lvds.c224 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_set_power()
235 } while (pp_status & PP_ON); in psb_intel_lvds_set_power()
323 } while ((pp_status & PP_ON) == 0); in psb_intel_lvds_restore()
329 } while (pp_status & PP_ON); in psb_intel_lvds_restore()
H A Doaktrail_lvds.c52 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); in oaktrail_lvds_set_power()
63 } while (pp_status & PP_ON); in oaktrail_lvds_set_power()
H A Dcdv_intel_lvds.c121 } while ((pp_status & PP_ON) == 0); in cdv_intel_lvds_set_power()
132 } while (pp_status & PP_ON); in cdv_intel_lvds_set_power()
H A Dpsb_intel_reg.h151 # define PP_ON (1 << 31) macro
H A Dcdv_intel_dp.c415 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE; in cdv_intel_edp_panel_on()
441 u32 pp, idle_off_mask = PP_ON ; in cdv_intel_edp_panel_off()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_pps_regs.h22 #define PP_ON REG_BIT(31) macro
H A Dintel_pps.c275 return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON; in pps_has_pp_on()
537 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
575 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
576 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
578 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
581 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1551 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", in pps_init_registers()
H A Dintel_lvds.c327 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) in intel_enable_lvds()
343 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) in intel_disable_lvds()
H A Dintel_display_power.c1218 intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, in assert_can_disable_lcpll()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c321 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) in intel_enable_lvds()
338 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) in intel_disable_lvds()
H A Dintel_dp.c984 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
1197 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
2890 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2891 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2893 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2896 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
7184 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", in intel_dp_init_panel_power_sequencer_registers()
H A Dintel_display_power.c4824 I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, in assert_can_disable_lcpll()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c378 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write()
385 ~(PP_ON | PP_SEQUENCE_POWER_DOWN in pch_pp_control_mmio_write()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write()
387 ~(PP_ON | PP_SEQUENCE_POWER_DOWN in pch_pp_control_mmio_write()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_reg.h5005 #define PP_ON REG_BIT(31) macro

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