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Searched refs:PORT_BASE (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c112 #define PORT_BASE (0x800) macro
114 #define PHY_CFG (PORT_BASE + 0x0)
119 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
126 #define PHY_CTRL (PORT_BASE + 0x14)
129 #define PHY_RATE_NEGO (PORT_BASE + 0x30)
130 #define PHY_PCN (PORT_BASE + 0x44)
131 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
132 #define SL_CONTROL (PORT_BASE + 0x94)
135 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
136 #define TX_ID_DWORD1 (PORT_BASE
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H A Dhisi_sas_v3_hw.c184 #define PORT_BASE (0x2000) macro
185 #define PHY_CFG (PORT_BASE + 0x0)
186 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
193 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
198 #define PHY_CTRL (PORT_BASE + 0x14)
203 #define SERDES_CFG (PORT_BASE + 0x1c)
206 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
217 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
218 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
219 #define SAS_BIST_ERR_CNT (PORT_BASE
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H A Dhisi_sas_v2_hw.c170 #define PORT_BASE (0x2000) macro
172 #define PHY_CFG (PORT_BASE + 0x0)
173 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
181 #define PHY_CTRL (PORT_BASE + 0x14)
184 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
185 #define SL_CFG (PORT_BASE + 0x84)
186 #define PHY_PCN (PORT_BASE + 0x44)
187 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
188 #define SL_CONTROL (PORT_BASE
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/kernel/linux/linux-6.6/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c112 #define PORT_BASE (0x800) macro
114 #define PHY_CFG (PORT_BASE + 0x0)
119 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
126 #define PHY_CTRL (PORT_BASE + 0x14)
129 #define PHY_RATE_NEGO (PORT_BASE + 0x30)
130 #define PHY_PCN (PORT_BASE + 0x44)
131 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
132 #define SL_CONTROL (PORT_BASE + 0x94)
135 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
136 #define TX_ID_DWORD1 (PORT_BASE
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H A Dhisi_sas_v2_hw.c170 #define PORT_BASE (0x2000) macro
172 #define PHY_CFG (PORT_BASE + 0x0)
173 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
181 #define PHY_CTRL (PORT_BASE + 0x14)
184 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
185 #define SL_CFG (PORT_BASE + 0x84)
186 #define PHY_PCN (PORT_BASE + 0x44)
187 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
188 #define SL_CONTROL (PORT_BASE
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H A Dhisi_sas_v3_hw.c186 #define PORT_BASE (0x2000) macro
187 #define PHY_CFG (PORT_BASE + 0x0)
188 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
195 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
200 #define PHY_CTRL (PORT_BASE + 0x14)
205 #define SERDES_CFG (PORT_BASE + 0x1c)
208 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
219 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
220 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
221 #define SAS_BIST_ERR_CNT (PORT_BASE
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/kernel/linux/linux-5.10/tools/testing/selftests/net/
H A Dpsock_fanout.c353 typeflags, (uint16_t)PORT_BASE, in test_datapath()
354 (uint16_t)(PORT_BASE + port_off)); in test_datapath()
369 pair_udp_open(fds_udp[0], PORT_BASE); in test_datapath()
370 pair_udp_open(fds_udp[1], PORT_BASE + port_off); in test_datapath()
H A Dpsock_lib.h21 #define PORT_BASE 8000 macro
H A Dpsock_tpacket.c229 pair_udp_open(udp_sock, PORT_BASE); in walk_v1_v2_rx()
590 pair_udp_open(udp_sock, PORT_BASE); in walk_v3_rx()
/kernel/linux/linux-6.6/tools/testing/selftests/net/
H A Dpsock_fanout.c417 typeflags, (uint16_t)PORT_BASE, in test_datapath()
418 (uint16_t)(PORT_BASE + port_off)); in test_datapath()
433 pair_udp_open(fds_udp[0], PORT_BASE); in test_datapath()
434 pair_udp_open(fds_udp[1], PORT_BASE + port_off); in test_datapath()
H A Dpsock_lib.h23 #define PORT_BASE 8000 macro
H A Dpsock_tpacket.c229 pair_udp_open(udp_sock, PORT_BASE); in walk_v1_v2_rx()
590 pair_udp_open(udp_sock, PORT_BASE); in walk_v3_rx()
/kernel/linux/linux-5.10/drivers/ata/
H A Dahci_ceva.c69 #define PORT_BASE 0x100 macro
182 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
/kernel/linux/linux-6.6/drivers/ata/
H A Dahci_ceva.c70 #define PORT_BASE 0x100 macro
183 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_regs.h58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) macro
59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_regs.h58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) macro
59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))

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