Searched refs:PLL_OUTCTRL (Results 1 - 6 of 6) sorted by relevance
| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| H A D | clk-pll.c | 20 #define PLL_OUTCTRL BIT(0) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
62 PLL_OUTCTRL); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
296 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_sr2_enable()
297 PLL_OUTCTRL); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
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| H A D | clk-hfpll.c | 15 #define PLL_OUTCTRL BIT(0) macro
84 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); in __clk_hfpll_enable()
98 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
115 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
207 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
234 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
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| H A D | clk-alpha-pll.c | 16 # define PLL_OUTCTRL BIT(0) macro
335 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_enable()
374 PLL_OUTCTRL, PLL_OUTCTRL); in clk_alpha_pll_enable()
397 mask = PLL_OUTCTRL; in clk_alpha_pll_disable()
771 return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL)); in trion_pll_is_enabled()
815 PLL_OUTCTRL, PLL_OUTCTRL); in clk_trion_pll_enable()
836 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1073 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) in alpha_pll_fabia_enable()
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| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| H A D | clk-pll.c | 20 #define PLL_OUTCTRL BIT(0) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
62 PLL_OUTCTRL); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
296 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_sr2_enable()
297 PLL_OUTCTRL); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
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| H A D | clk-hfpll.c | 15 #define PLL_OUTCTRL BIT(0) macro
87 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); in __clk_hfpll_enable()
101 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
118 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
210 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
237 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
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| H A D | clk-alpha-pll.c | 17 # define PLL_OUTCTRL BIT(0) macro
492 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_enable()
531 PLL_OUTCTRL, PLL_OUTCTRL); in clk_alpha_pll_enable()
554 mask = PLL_OUTCTRL; in clk_alpha_pll_disable()
928 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); in trion_pll_is_enabled()
972 PLL_OUTCTRL, PLL_OUTCTRL); in clk_trion_pll_enable()
993 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1220 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) in alpha_pll_fabia_enable()
[all...] |
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