Searched refs:PLL_BYPASSNL (Results 1 - 6 of 6) sorted by relevance
| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| H A D | clk-pll.c | 21 #define PLL_BYPASSNL BIT(1) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
41 PLL_BYPASSNL); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
274 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_sr2_enable()
275 PLL_BYPASSNL); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
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| H A D | clk-hfpll.c | 16 #define PLL_BYPASSNL BIT(1) macro
63 regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); in __clk_hfpll_enable()
98 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
115 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
207 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
234 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
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| H A D | clk-alpha-pll.c | 17 # define PLL_BYPASSNL BIT(1) macro
335 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_enable()
353 PLL_BYPASSNL, PLL_BYPASSNL); in clk_alpha_pll_enable()
404 mask = PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_disable()
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| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| H A D | clk-pll.c | 21 #define PLL_BYPASSNL BIT(1) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
41 PLL_BYPASSNL); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
274 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_sr2_enable()
275 PLL_BYPASSNL); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
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| H A D | clk-hfpll.c | 16 #define PLL_BYPASSNL BIT(1) macro
63 regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); in __clk_hfpll_enable()
101 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
118 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
210 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
237 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
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| H A D | clk-alpha-pll.c | 18 # define PLL_BYPASSNL BIT(1) macro
492 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_enable()
510 PLL_BYPASSNL, PLL_BYPASSNL); in clk_alpha_pll_enable()
561 mask = PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_disable()
1957 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
1988 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
2041 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2328 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTR in clk_rivian_evo_pll_configure()
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