Searched refs:PHY_CSR5 (Results 1 - 12 of 12) sorted by relevance
| /kernel/linux/linux-5.10/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2500usb.h | 499 * PHY_CSR5: BBP pre-TX CCK.
501 #define PHY_CSR5 0x04ca macro
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| H A D | rt73usb.h | 520 * PHY_CSR5: RX to TX signal switch timing control.
522 #define PHY_CSR5 0x3094 macro
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| H A D | rt61pci.h | 605 * PHY_CSR5: RX to TX signal switch timing control.
607 #define PHY_CSR5 0x3094 macro
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| H A D | rt2500usb.c | 517 csr5 = rt2500usb_register_read(rt2x00dev, PHY_CSR5); in rt2500usb_config_ant()
578 rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5); in rt2500usb_config_ant()
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| H A D | rt73usb.c | 1237 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); in rt73usb_init_registers()
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| H A D | rt61pci.c | 1503 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); in rt61pci_init_registers()
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| /kernel/linux/linux-6.6/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2500usb.h | 499 * PHY_CSR5: BBP pre-TX CCK.
501 #define PHY_CSR5 0x04ca macro
|
| H A D | rt73usb.h | 520 * PHY_CSR5: RX to TX signal switch timing control.
522 #define PHY_CSR5 0x3094 macro
|
| H A D | rt61pci.h | 605 * PHY_CSR5: RX to TX signal switch timing control.
607 #define PHY_CSR5 0x3094 macro
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| H A D | rt2500usb.c | 517 csr5 = rt2500usb_register_read(rt2x00dev, PHY_CSR5); in rt2500usb_config_ant()
578 rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5); in rt2500usb_config_ant()
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| H A D | rt73usb.c | 1237 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); in rt73usb_init_registers()
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| H A D | rt61pci.c | 1503 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); in rt61pci_init_registers()
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