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Searched refs:PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_resource.h79 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_sh_mask.h1703 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x1 macro
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H A Ddce_12_0_sh_mask.h2786 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_sh_mask.h1703 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x1 macro
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H A Ddce_12_0_sh_mask.h2786 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_0_sh_mask.h703 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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H A Ddcn_1_0_sh_mask.h2139 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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H A Ddcn_3_0_0_sh_mask.h693 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h2139 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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H A Ddcn_3_1_6_sh_mask.h1467 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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H A Ddcn_3_0_0_sh_mask.h694 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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H A Ddcn_2_0_0_sh_mask.h703 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L macro
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