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Searched refs:OTG (Results 1 - 25 of 46) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.h32 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
33 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
34 SRI(OTG_VREADY_PARAM, OTG, inst),\
35 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
36 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
40 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
41 SRI(OTG_H_TOTAL, OTG, ins
[all...]
H A Ddcn31_dccg.h45 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
46 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
107 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
108 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
109 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
112 DCCG_SFII(OTG, PIXEL_RATE_CNT
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.h33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
35 SRI(OTG_VREADY_PARAM, OTG, inst),\
36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, ins
[all...]
H A Ddcn314_dccg.h52 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
53 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
54 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
55 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
112 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
114 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
115 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
116 DCCG_SFII(OTG, PIXEL_RATE_CNT
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.h34 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
35 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
36 SRI(OTG_VREADY_PARAM, OTG, inst),\
37 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
41 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
42 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
43 SRI(OTG_H_TOTAL, OTG, ins
[all...]
H A Ddcn30_dccg.h41 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
42 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
43 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
44 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.h33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
35 SRI(OTG_VREADY_PARAM, OTG, inst),\
36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, ins
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
75 SRII(PIXEL_RATE_CNTL, OTG, 3),\
76 SRII(PIXEL_RATE_CNTL, OTG, 4),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
85 SRII(PIXEL_RATE_CNTL, OTG, 0),\
86 SRII(PIXEL_RATE_CNTL, OTG, 1)
98 SRII(PIXEL_RATE_CNTL, OTG, 0),\
99 SRII(PIXEL_RATE_CNTL, OTG,
[all...]
H A Ddce_hwseq.h224 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
225 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
226 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
227 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
258 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
259 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
260 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
261 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
262 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
263 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG,
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
46 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
49 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXE
[all...]
H A Ddcn20_optc.h33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
39 SRI(OTG_CRC_CNTL2, OTG, inst),\
45 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
46 SRI(OTG_DRR_CONTROL, OTG, inst)
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.h80 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
84 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
85 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
86 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
87 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
88 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
89 DCCG_SFII(OTG, PIXEL_RATE_CNT
[all...]
H A Ddcn32_resource.h190 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \
191 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \
192 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \
193 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index) \
1034 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
1035 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
1036 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
1037 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
1038 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
1039 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, ins
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.h35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
37 SRI(OTG_VREADY_PARAM, OTG, inst),\
38 SRI(OTG_BLANK_CONTROL, OTG, inst),\
39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_BLANK_START_END, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, ins
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.h35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
37 SRI(OTG_VREADY_PARAM, OTG, inst),\
38 SRI(OTG_BLANK_CONTROL, OTG, inst),\
39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_BLANK_START_END, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, ins
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
75 SRII(PIXEL_RATE_CNTL, OTG, 3),\
76 SRII(PIXEL_RATE_CNTL, OTG, 4),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
89 SRII(PIXEL_RATE_CNTL, OTG, 0),\
90 SRII(PIXEL_RATE_CNTL, OTG, 1),\
91 SRII(PIXEL_RATE_CNTL, OTG, 2),\
92 SRII(PIXEL_RATE_CNTL, OTG,
[all...]
H A Ddce_hwseq.h195 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
196 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
197 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
198 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
231 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
232 HWSEQ_PHYPLL_REG_LIST_3(OTG), \
251 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
252 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
253 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
254 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG,
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_dccg.h20 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
21 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
41 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
42 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
43 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
44 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXE
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.h33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_optc.h33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
39 SRI(OTG_CRC_CNTL2, OTG, inst),\
45 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c193 IRQ_REG_ENTRY(OTG, reg_num,\
204 IRQ_REG_ENTRY(OTG, reg_num,\
211 IRQ_REG_ENTRY(OTG, reg_num,\
219 IRQ_REG_ENTRY(OTG, reg_num,\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c162 IRQ_REG_ENTRY(OTG, reg_num,\
170 IRQ_REG_ENTRY(OTG, reg_num,\
178 IRQ_REG_ENTRY(OTG, reg_num,\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c244 IRQ_REG_ENTRY(OTG, reg_num,\
252 IRQ_REG_ENTRY(OTG, reg_num,\
260 IRQ_REG_ENTRY(OTG, reg_num,\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c278 IRQ_REG_ENTRY(OTG, reg_num,\
286 IRQ_REG_ENTRY(OTG, reg_num,\
301 IRQ_REG_ENTRY(OTG, reg_num,\
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c273 IRQ_REG_ENTRY(OTG, reg_num,\
281 IRQ_REG_ENTRY(OTG, reg_num,\
289 IRQ_REG_ENTRY(OTG, reg_num,\

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