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Searched refs:NPS_CORE_INT (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/crypto/cavium/nitrox/
H A Dnitrox_isr.c46 value = nitrox_read_csr(ndev, NPS_CORE_INT); in clear_nps_core_err_intr()
47 nitrox_write_csr(ndev, NPS_CORE_INT, value); in clear_nps_core_err_intr()
H A Dnitrox_csr.h119 #define NPS_CORE_INT 0x10000A0 macro
732 * NPS_CORE_INT[HOST_NPS_WR_ERR].
734 * NPS_CORE_INT[NPCO_DMA_MALFORM].
736 * NPS_CORE_INT[EXEC_WR_TIMEOUT].
738 * NPS_CORE_INT[HOST_WR_TIMEOUT].
740 * NPS_CORE_INT[HOST_WR_ERR]
843 * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO
844 * NPS_CORE_INT and corresponding NSP_CORE_INT_ENA_W1C bits are both set
/kernel/linux/linux-6.6/drivers/crypto/cavium/nitrox/
H A Dnitrox_isr.c47 value = nitrox_read_csr(ndev, NPS_CORE_INT); in clear_nps_core_err_intr()
48 nitrox_write_csr(ndev, NPS_CORE_INT, value); in clear_nps_core_err_intr()
H A Dnitrox_csr.h119 #define NPS_CORE_INT 0x10000A0 macro
732 * NPS_CORE_INT[HOST_NPS_WR_ERR].
734 * NPS_CORE_INT[NPCO_DMA_MALFORM].
736 * NPS_CORE_INT[EXEC_WR_TIMEOUT].
738 * NPS_CORE_INT[HOST_WR_TIMEOUT].
740 * NPS_CORE_INT[HOST_WR_ERR]
843 * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO
844 * NPS_CORE_INT and corresponding NSP_CORE_INT_ENA_W1C bits are both set

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