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Help
Searched
refs:NPCM7XX_REG_TCSR0
(Results
1 - 2
of
2
) sorted by relevance
/kernel/linux/linux-5.10/drivers/clocksource/
H
A
D
timer-npcm7xx.c
22
#define
NPCM7XX_REG_TCSR0
0x0 /* Timer 0 Control and Status Register */
macro
61
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_resume()
63
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_resume()
73
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_shutdown()
75
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_shutdown()
85
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_oneshot()
88
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_oneshot()
100
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_periodic()
103
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_periodic()
115
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_clockevent_set_next_event()
[all...]
/kernel/linux/linux-6.6/drivers/clocksource/
H
A
D
timer-npcm7xx.c
22
#define
NPCM7XX_REG_TCSR0
0x0 /* Timer 0 Control and Status Register */
macro
61
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_resume()
63
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_resume()
73
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_shutdown()
75
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_shutdown()
85
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_oneshot()
88
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_oneshot()
100
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_periodic()
103
writel(val, timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_timer_periodic()
115
val = readl(timer_of_base(to) +
NPCM7XX_REG_TCSR0
);
in npcm7xx_clockevent_set_next_event()
[all...]
Completed in 1 milliseconds