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Searched refs:MV88E6XXX_G1_CTL1 (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/
H A Dglobal1.c115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_reset()
122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_reset()
139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6250_g1_reset()
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6250_g1_reset()
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_enable()
174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_enable()
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_disable()
192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_disable()
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_set_max_frame_size()
215 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, va in mv88e6185_g1_set_max_frame_size()
[all...]
H A Dglobal1.h55 #define MV88E6XXX_G1_CTL1 0x04 macro
H A Dchip.c170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); in mv88e6xxx_g1_irq_thread_work()
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg); in mv88e6xxx_g1_irq_bus_sync_unlock()
213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); in mv88e6xxx_g1_irq_bus_sync_unlock()
253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); in mv88e6xxx_g1_irq_free_common()
255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); in mv88e6xxx_g1_irq_free_common()
296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); in mv88e6xxx_g1_irq_setup_common()
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); in mv88e6xxx_g1_irq_setup_common()
315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); in mv88e6xxx_g1_irq_setup_common()
/kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/
H A Dglobal1.c115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_reset()
122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_reset()
139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6250_g1_reset()
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6250_g1_reset()
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_enable()
174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_enable()
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_disable()
192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_disable()
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_set_max_frame_size()
215 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, va in mv88e6185_g1_set_max_frame_size()
[all...]
H A Dglobal1.h57 #define MV88E6XXX_G1_CTL1 0x04 macro
H A Dchip.c185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); in mv88e6xxx_g1_irq_thread_work()
221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg); in mv88e6xxx_g1_irq_bus_sync_unlock()
228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); in mv88e6xxx_g1_irq_bus_sync_unlock()
268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); in mv88e6xxx_g1_irq_free_common()
270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); in mv88e6xxx_g1_irq_free_common()
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); in mv88e6xxx_g1_irq_setup_common()
317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); in mv88e6xxx_g1_irq_setup_common()
330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); in mv88e6xxx_g1_irq_setup_common()

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