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Searched refs:MSR_TYPE_RW (Results 1 - 7 of 7) sorted by relevance

/kernel/linux/linux-6.6/arch/x86/kvm/vmx/
H A Dpmu_intel.c673 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
674 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
676 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
679 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
680 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
H A Dvmx.c2207 MSR_TYPE_RW); in vmx_set_msr()
2307 MSR_TYPE_RW); in vmx_set_msr()
4090 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW, in vmx_update_msr_bitmap_x2apic()
4094 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW); in vmx_update_msr_bitmap_x2apic()
4098 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW); in vmx_update_msr_bitmap_x2apic()
4108 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
4109 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
4110 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
4111 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
4113 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, fla in pt_update_intercept_for_msr()
[all...]
H A Dvmx.h21 #define MSR_TYPE_RW 3 macro
H A Dnested.c646 MSR_FS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
649 MSR_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
652 MSR_KERNEL_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
655 MSR_IA32_SPEC_CTRL, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
/kernel/linux/linux-5.10/arch/x86/kvm/vmx/
H A Dvmx.c2150 MSR_TYPE_RW); in vmx_set_msr()
3957 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW, in vmx_update_msr_bitmap_x2apic()
3961 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW); in vmx_update_msr_bitmap_x2apic()
3988 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
3989 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
3990 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
3991 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
3993 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
3994 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); in pt_update_intercept_for_msr()
7080 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW); in vmx_create_vcpu()
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H A Dvmx.h22 #define MSR_TYPE_RW 3 macro
H A Dnested.c624 MSR_FS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
627 MSR_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
630 MSR_KERNEL_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()

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