Searched refs:MSR_IA32_PEBS_ENABLE (Results 1 - 19 of 19) sorted by relevance
| /kernel/linux/linux-6.6/arch/x86/kvm/vmx/ |
| H A D | pmu_intel.c | 209 case MSR_IA32_PEBS_ENABLE: in intel_is_valid_msr()
358 case MSR_IA32_PEBS_ENABLE: in intel_pmu_get_msr()
407 case MSR_IA32_PEBS_ENABLE: in intel_pmu_set_msr()
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| H A D | vmx.c | 1068 case MSR_IA32_PEBS_ENABLE: in add_atomic_switch_msr()
1074 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); in add_atomic_switch_msr()
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| /kernel/linux/linux-5.10/arch/x86/xen/ |
| H A D | pmu.c | 150 case MSR_IA32_PEBS_ENABLE: in is_intel_pmu_msr()
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| /kernel/linux/linux-6.6/arch/x86/xen/ |
| H A D | pmu.c | 159 case MSR_IA32_PEBS_ENABLE: in is_intel_pmu_msr()
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| /kernel/linux/linux-5.10/arch/x86/events/intel/ |
| H A D | ds.c | 1184 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
1194 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
1202 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); in intel_pmu_pebs_disable_all()
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| H A D | p4.c | 47 * written into MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT
899 * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0); in p4_pmu_disable_pebs()
946 (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); in p4_pmu_enable_pebs()
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| H A D | core.c | 2039 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; in intel_pmu_nhm_workaround()
2642 * MSR_IA32_PEBS_ENABLE is not updated. Because the in handle_pmi_common()
2647 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in handle_pmi_common()
3725 arr[1].msr = MSR_IA32_PEBS_ENABLE; in intel_guest_get_msrs()
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| H A D | msr-index.h | 248 #define MSR_IA32_PEBS_ENABLE 0x000003f1 macro
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| /kernel/linux/linux-5.10/tools/arch/x86/include/asm/ |
| H A D | msr-index.h | 222 #define MSR_IA32_PEBS_ENABLE 0x000003f1 macro
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| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| H A D | msr-index.h | 261 #define MSR_IA32_PEBS_ENABLE 0x000003f1 macro
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| /kernel/linux/linux-6.6/tools/arch/x86/include/asm/ |
| H A D | msr-index.h | 253 #define MSR_IA32_PEBS_ENABLE 0x000003f1 macro
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| /kernel/linux/linux-6.6/arch/x86/events/intel/ |
| H A D | ds.c | 1422 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
1432 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
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| H A D | p4.c | 47 * written into MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT
899 * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0); in p4_pmu_disable_pebs()
946 (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); in p4_pmu_enable_pebs()
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| H A D | core.c | 2328 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; in intel_pmu_nhm_workaround()
3015 * MSR_IA32_PEBS_ENABLE is not updated. Because the in handle_pmi_common()
3020 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in handle_pmi_common()
4091 .msr = MSR_IA32_PEBS_ENABLE, in intel_guest_get_msrs()
4117 .msr = MSR_IA32_PEBS_ENABLE, in intel_guest_get_msrs()
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| /kernel/linux/linux-6.6/arch/x86/events/ |
| H A D | perf_event.h | 1443 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); in __intel_pmu_pebs_disable_all()
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| H A D | core.c | 1548 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); in perf_event_print_debug()
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| /kernel/linux/linux-5.10/arch/x86/events/ |
| H A D | core.c | 1513 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); in perf_event_print_debug()
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| /kernel/linux/linux-5.10/arch/x86/kvm/vmx/ |
| H A D | vmx.c | 1055 case MSR_IA32_PEBS_ENABLE: in add_atomic_switch_msr()
1061 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); in add_atomic_switch_msr()
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| /kernel/linux/linux-6.6/arch/x86/kvm/ |
| H A D | x86.c | 1474 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
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